Datasheet

The GCLK block diagram is shown below:
Figure 14-2. Generic Clock Controller Block Diagram
Generic Clock Generator 0
GCLK_IO[0]
(I/O input)
Clock
Divider &
Masker
Clock Sources
GCLKGEN[0]
GCLK_IO[1]
(I/O input)
GCLKGEN[1]
GCLK_IO[n]
(I/O input)
GCLKGEN[n]
Clock
Gate
Peripheral Channel 0
GCLK_PERIPH[0]
Clock
Gate
Peripheral Channel 1
Clock
Gate
Peripheral Channel n
GCLKGEN[n:0]
GCLK_MAIN
GCLK_IO[1]
(I/O output)
GCLK_IO[0]
(I/O output)
GCLK_IO[n]
(I/O output)
Generic Clock Generator 1
Clock
Divider &
Masker
Generic Clock Generator n
Clock
Divider &
Masker
GCLK_PERIPH[1]
GCLK_PERIPH[n]
14.4 Signal Description
Table 14-1. GCLK Signal Description
Signal Name Type Description
GCLK_IO[7:0] Digital I/O Clock source for Generators
when input
Generic Clock signal when output
Note: One signal can be mapped on several pins.
Related Links
6. I/O Multiplexing and Considerations
14.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
14.5.1 I/O Lines
Using the GCLK I/O lines requires the I/O pins to be configured.
Related Links
32. PORT - I/O Pin Controller
14.5.2 Power Management
The GCLK can operate in sleep modes, if required. Refer to the Sleep mode description in the Power
Manager (PM) section.
Related Links
18. PM – Power Manager
SAM D5x/E5x Family Data Sheet
GCLK - Generic Clock Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 153