Datasheet

14. GCLK - Generic Clock Controller
14.1 Overview
Depending on the application, peripherals may require specific clock frequencies to operate correctly. The
Generic Clock controller (GCLK) features 12 Generic Clock Generators [11:0] that can provide a wide
range of clock frequencies.
Generators can be set to use different external and internal oscillators as source. The clock of each
Generator can be divided. The outputs from the Generators are used as sources for the Peripheral
Channels, which provide the Generic Clock (GCLK_PERIPH) to the peripheral modules, as shown in
Figure 14-2. The number of Peripheral Clocks depends on how many peripherals the device has.
Note: The Generator 0 is always the direct source of the GCLK_MAIN signal.
14.2 Features
• Provides a device-defined, configurable number of Peripheral Channel clocks
• Wide frequency range:
– Various clock sources
– Embedded dividers
14.3 Block Diagram
The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be
seen in Device Clocking Diagram.
Figure 14-1. Device Clocking Diagram
GCLK_IO
Generic Clock Generator
OSCCTRL
Clock
Divider &
Masker
Clock
Gate
Peripheral Channel
GCLK_PERIPH
PERIPHERAL
GENERIC CLOCK CONTROLLER
MCLK
GCLK_MAIN
XOSC1
OSC32KCTRL
OSCULP32K
XOSC32K
XOSC0
FDPLL0
DFLL
FDPLL1
SAM D5x/E5x Family Data Sheet
GCLK - Generic Clock Controller
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 152