Datasheet

REGC (16-bit access) can be written without affecting REGA or REGB. If REGC is written to in two
consecutive 8-bit accesses without waiting for synchronization, the second write attempt will be discarded
and an error is generated through the PAC.
A 32-bit access to offset 0x00 will write all three registers. Note that REGA, REGB and REGC can be
updated at different times because of independent write synchronization.
13.3.3 General Read Synchronization
Read-synchronized registers are synchronized each time the register value is updated but the
corresponding SYNCBUSY bits are not set. Reading a read-synchronized register does not start a new
synchronization, it returns the last synchronized value.
Note: The corresponding bits in SYNCBUSY will automatically be set when the device wakes up from
sleep because read-synchronized registers need to be synchronized. Therefore reading a read-
synchronized register before its corresponding SYNCBUSY bit is cleared will return the last synchronized
value before sleep mode.
However, if a register is also write-synchronized, any write access while the SYNCBUSY bit is set will be
executed successfully. If concurrent read and write access is detected, the read is discarded and a new
synchronization will start.
13.3.4 Completion of Synchronization
In order to check if synchronization is complete, the user can either poll the relevant bits in SYNCBUSY
or use the Synchronisation Ready interrupt (if available). The Synchronization Ready interrupt flag will be
set when all ongoing synchronizations are complete, i.e. when all bits in SYNCBUSY are '0'.
13.3.5 Write Synchronization for CTRLA.ENABLE
Setting the Enable bit in a module's Control A register (CTRLA.ENABLE) will trigger write-synchronization
and set SYNCBUSY.ENABLE.
CTRLA.ENABLE will read its new value immediately after being written.
SYNCBUSY.ENABLE will be cleared by hardware when the operation is complete.
The Synchronization Ready interrupt (if available) cannot be used to enable write-synchronization.
13.3.6 Write-Synchronization for Software Reset Bit
Setting the Software Reset bit in CTRLA (CTRLA.SWRST=1) will trigger write-synchronization and set
SYNCBUSY.SWRST. When writing a ‘1’ to the CTRLA.SWRST bit it will immediately read as ‘1’.
CTRL.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset.
Writing a '0' to the CTRL.SWRST bit has no effect.
The Ready interrupt (if available) cannot be used for Software Reset write-synchronization.
Note: Not all peripherals have the SWRST bit in the respective CTRLA register.
13.3.7 Synchronization Delay
The synchronization will delay write and read accesses by a certain amount. This delay D is within the
range of:
5×P
GCLK
+ 2×P
APB
< D < 6×P
GCLK
+ 3×P
APB
Where P
GCLK
is the period of the generic clock and P
APB
is the period of the peripheral bus clock. A
normal peripheral bus register access duration is 2×P
APB
.
SAM D5x/E5x Family Data Sheet
Clock System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 149