Datasheet

Figure 13-3. Register Synchronization Overview
Synchronous Domain
(CLK_APB)
Asynchronous Domain
(GCLK )
Non Sync’d reg
Periperal Bus
Write-Sync’d reg
SYNCBUSY
R/W-Sync’d reg
Sync
Sync
Read-Sync’d reg
Sync
Write-only register
Read-only register
R/W register
Write-Sync’d reg
Sync
R/W register
Non Sync’d reg
Read-only register
Sync
INTFLAG
13.3.2 General Write Synchronization
Write-Synchronization is triggered by writing to a register in the peripheral clock domain (GCLK). The
respective bit in the Synchronization Busy register (SYNCBUSY) will be set when the write-
synchronization starts and cleared when the write-synchronization is complete. Refer also to 13.3.7
Synchronization Delay.
When write-synchronization is ongoing for a register, any subsequent write attempts to this register will be
discarded, and an error will be reported though the Peripheral Access Controller (PAC).
Example:
REGA, REGB are 8-bit core registers. REGC is a 16-bit core register.
Offset Register
0x00 REGA
0x01 REGB
0x02 REGC
0x03
Synchronization is per register, so multiple registers can be synchronized in parallel. Consequently, after
REGA (8-bit access) was written, REGB (8-bit access) can be written immediately without error.
SAM D5x/E5x Family Data Sheet
Clock System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 148