Datasheet

– Generic Clock Generators: These are programmable prescalers that can use any of the system
clock sources as a time base. The Generic Clock Generator 0 generates the clock signal
GCLK_MAIN, which is used by the Power Manager and the Main Clock (MCLK) module, which
in turn generates synchronous clocks.
– Generic Clocks: These are clock signals generated by Generic Clock Generators and output by
the Peripheral Channels, and serve as clocks for the peripherals of the system. Multiple
instances of a peripheral will typically have a separate Generic Clock for each instance. Generic
Clock 0 serves as the clock source for the DFLL48M clock input (when multiplying another clock
source).
• Main Clock Controller (MCLK)
– The MCLK generates and controls the synchronous clocks on the system. This includes the
CPU, bus clocks (APB, AHB) as well as the synchronous (to the CPU) user interfaces of the
peripherals. It contains clock masks that can turn on/off the user interface of a peripheral as well
as prescalers for the CPU and bus clocks.
The next figure shows an example where SERCOM0 is clocked by the DFLL48M in open
loop mode. The DFLL48M is enabled, the Generic Clock Generator 1 uses the DFLL48M
as its clock source and feeds into Peripheral Channel 7. The Generic Clock 7, also called
GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0 interface,
clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the
MCLK.
Figure 13-2. Example of SERCOM Clock
OSCCTRL
DFLL48M
Generic Clock
Generator 1
Peripheral
Channel 7
SERCOM 0
Syncronous Clock
Controller
MCLK
CLK_SERCOM0_APB
GCLK_SERCOM0_CORE
GCLK
To customize the clock distribution, refer to these registers and bit fields:
• The source oscillator for a generic clock generator n is selected by writing to the
Source bit field in the Generator Control n register (GCLK.GENCTRLn.SRC).
• A Peripheral Channel m can be configured to use a specific Generic Clock
Generator by writing to the Generic Clock Generator bit field in the respective
Peripheral Channel m register (GCLK.PCHCTRLm.GEN)
• The Peripheral Channel number, m, is fixed for a given peripheral. See the Mapping
table in the description of GCLK.PCHCTRLm.
• The AHB clocks are enabled and disabled by writing to the respective bit in the AHB
Mask register (MCLK.AHBMASK).
• The APB clocks are enabled and disabled by writing to the respective bit in the APB
x Mask registers (MCLK.APBxMASK).
Related Links
13.7 Clocks after Reset
SAM D5x/E5x Family Data Sheet
Clock System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 146