Datasheet

Table Of Contents
13. Clock System
This chapter summarizes the clock distribution and terminology in the SAM D5x/E5x device. It does not
explain every detail of its configuration. For in-depth documentation, see the respective peripherals
descriptions and the Generic Clock documentation.
Related Links
14. GCLK - Generic Clock Controller
15. MCLK – Main Clock
13.1 Clock Distribution
Figure 13-1. Clock Distribution
GCLK Generator 0
OSCCTRL
GCLK
GCLK Generator 1
GCLK Generator x
Peripheral Channel 0
(DFLL48M Reference)
Peripheral Channel [2:1]
(FDPLL200M Reference)
Peripheral z
Peripheral 0
Syncronous Clock
Controller
MCLK
AHB/APB System Clocks
GCLK_MAIN
DFLL48M
XOSCn
Generic
Clocks
OSCK32CTRL
OSCULP32K
XOSC32K
Peripheral Channel 4
GCLK_DFLL48M_REF
GCLK_DPLLn
Peripheral Channel y
GCLK_DPLLn_32K
GCLK_DPLLn
GCLK_DPLLn_32K
RTC
CLK_RTC_OSC
CLK_WDT_OSC
Peripheral Channel 3
(FDPLL200M lock ref)
WDT
32kHz
1kHz
32kHz
1kHz
CLK_ULP32K
EIC
FDPLL200M
GMAC
USB
Generic Clock
GTXCK
GRXCK
PCC
CLK
The SAM D5x/E5x clock system consists of:
Clock sources, i.e. oscillators controlled by OSCCTRL and OSC32KCTRL
A clock source provides a time base that is used by other components, such as Generic Clock
Generators. Example clock sources are the external crystal oscillator (XOSC) and the Digital
Frequency Locked Loop (DFLL48M).
Generic Clock Controller (GCLK), which generates, controls and distributes the asynchronous clock
consisting of:
SAM D5x/E5x Family Data Sheet
Clock System
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 145