Datasheet

Table Of Contents

42.8.5 Interrupt Flag Status and Clear

Name: INTFLAG

Offset: 0x07

Reset: 0x00

Bit 7 6 5 4 3 2 1 0

GFMCMP ENCCMP

Access

R/W R/W

Reset 0 0

Bit 1 – GFMCMP GF Multiplication Complete

This flag is cleared by writing a '1' to it.

This flag is set when GHASH value is available on the Galois Hash Registers (GHASHx) in GCM mode.

Writing a '0' to this bit has no effect.

This flag is also automatically cleared in the following cases.

1. Manual encryption/decryption occurs (START in CTRLB register).

2. Reading from the GHASHx register.

Bit 0 – ENCCMP Encryption Complete

This flag is cleared by writing a '1' to it.

This flag is set when encryption/decryption is complete and valid data is available on the Data Register.

Writing a '0' to this bit has no effect.

This flag is also automatically cleared in the following cases:

1. Manual encryption/decryption occurs (START in CTRLA register). (This feature is needed only if we

do not support double buffering of DATA registers).

2. Reading from the data register (DATAx) when LOD = 0.

3. Writing into the data register (DATAx) when LOD = 1.

4. Reading from the Hash Key register (HASHKEYx).

SAM D5x/E5x Family Data Sheet

AES – Advanced Encryption Standard

Datasheet

DS60001507E-page 1433