Datasheet

...........continued
Offset Name Bit Pos.
0x68 HASHKEY3
7:0 HASHKEY[7:0]
15:8 HASHKEY[15:8]
23:16 HASHKEY[23:16]
31:24 HASHKEY[31:24]
0x6C GHASH0
7:0 GHASH[7:0]
15:8 GHASH[15:8]
23:16 GHASH[23:16]
31:24 GHASH[31:24]
0x70 GHASH1
7:0 GHASH[7:0]
15:8 GHASH[15:8]
23:16 GHASH[23:16]
31:24 GHASH[31:24]
0x74 GHASH2
7:0 GHASH[7:0]
15:8 GHASH[15:8]
23:16 GHASH[23:16]
31:24 GHASH[31:24]
0x78 GHASH3
7:0 GHASH[7:0]
15:8 GHASH[15:8]
23:16 GHASH[23:16]
31:24 GHASH[31:24]
0x7C
...
0x7F
Reserved
80 CIPLEN
7:0 CIPLEN[7:0]
15:8 CIPLEN[15:8]
23:16 CIPLEN[23:16]
31:24 CIPLEN[31:24]
0x84 RANDSEED
7:0 RANDSEED[7:0]
15:8 RANDSEED[15:8]
23:16 RANDSEED[23:16]
31:24 RANDSEED[31:24]
42.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 42.5.8 Register Access Protection.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
SAM D5x/E5x Family Data Sheet
AES – Advanced Encryption Standard
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1426