Datasheet

42.5.7 Debug Operation
When the CPU is halted in debug mode, the AES module continues normal operation. If the AES module
is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar,
improper operation or data loss may result during debugging. The AES module can be forced to halt
operation during debugging.
42.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC),
except the
following register:
• Interrupt Flag Register (INTFLAG)
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to PAC - Peripheral
Access Controller chapter for details.
Related Links
27. PAC - Peripheral Access Controller
42.5.9 Analog Connections
Not applicable.
42.6 Functional Description
42.6.1 Principle of Operation
The following is a high level description of the algorithm. These are the steps:
• KeyExpansion: Round keys are derived from the cipher key using Rijndael's key schedule.
• InitialRound:
– AddRoundKey: Each byte of the state is combined with the round key using bitwise XOR.
• Rounds:
– SubBytes: A non-linear substitution step where each byte is replaced with another according to a
lookup table.
– ShiftRows: A transposition step where each row of the state is shifted cyclically a certain number
of steps.
– MixColumns: A mixing operation which operates on the columns of the state, combining the four
bytes in each column.
– AddRoundKey
• Final Round (no MixColumns):
– SubBytes
– ShiftRows
– AddRoundKey
The relationship between the module's clock frequency and throughput (in bytes per second) is given by:
Clock Frequency = (Throughput/2) x (Nr+1) for 2 byte parallel processing
Clock Frequency = (Throughput/4) x (Nr+1) for 4 byte parallel processing
SAM D5x/E5x Family Data Sheet
AES – Advanced Encryption Standard
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1415