Datasheet

42.4 Signal Description
Not applicable.
42.5 Product Dependencies
In order to use this AES module, other parts of the system must be configured correctly, as described
below.
42.5.1 I/O Lines
Not applicable.
42.5.2 Power Management
The AES will continue to operate in Standby sleep mode, if it's source clock is running.
The AES interrupts can be used to wake up the device from Standby sleep mode. Refer to the Power
Manager chapter for details on the different sleep modes.
AES is clocked only on the following conditions:
• When the DMA is enabled.
• Whenever there is an APB access for any read and write operation to the AES registers. (Not in
Standby sleep mode.)
• When the AES is enabled & encryption/decryption is ongoing.
42.5.3 Clocks
The AES bus clock (CLK_AES_APB) can be enabled and disabled in the Main Clock module, and the
default state of CLK_AES_APB can be found in Peripheral Clock Masking. The module is fully clocked by
CLK_AES_APB.
Related Links
15.6.2.6 Peripheral Clock Masking
42.5.4 DMA
The AES has two DMA request lines; one for input data, and one for output data. They are both
connected to the DMA Controller (DMAC). These DMA request triggers will be acknowledged by the
DMAC ACK signals. Using the AES DMA requests requires the DMA Controller to be configured first.
Refer to the device DMA documentation.
42.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the AES interrupt requires the
interrupt controller to be configured first. Refer to the Processor and Architecture chapter for details.
All the AES interrupts are synchronous wake-up sources. See Sleep Mode Controller for details.
Related Links
18.6.3.3 Sleep Mode Controller
42.5.6 Events
Not applicable.
SAM D5x/E5x Family Data Sheet
AES – Advanced Encryption Standard
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1414