Datasheet

41.7 Register Summary
Offset Name Bit Pos.
0x00 CTRL 7:0 RUNSTDBY ENABLE SWRST
0x01
...
0x03
Reserved
0x04 SEQCTRL0 7:0 SEQSEL[3:0]
0x05 SEQCTRL1 7:0 SEQSEL[3:0]
0x06
...
0x07
Reserved
0x08 LUTCTRL0
7:0 EDGESEL FILTSEL[1:0] ENABLE
15:8 INSELx[3:0] INSELx[3:0]
23:16 LUTEO LUTEI INVEI INSELx[3:0]
31:24 TRUTH[7:0]
0x0C LUTCTRL1
7:0 EDGESEL FILTSEL[1:0] ENABLE
15:8 INSELx[3:0] INSELx[3:0]
23:16 LUTEO LUTEI INVEI INSELx[3:0]
31:24 TRUTH[7:0]
0x10 LUTCTRL2
7:0 EDGESEL FILTSEL[1:0] ENABLE
15:8 INSELx[3:0] INSELx[3:0]
23:16 LUTEO LUTEI INVEI INSELx[3:0]
31:24 TRUTH[7:0]
0x14 LUTCTRL3
7:0 EDGESEL FILTSEL[1:0] ENABLE
15:8 INSELx[3:0] INSELx[3:0]
23:16 LUTEO LUTEI INVEI INSELx[3:0]
31:24 TRUTH[7:0]
41.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 41.5.8 Register Access Protection.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
SAM D5x/E5x Family Data Sheet
CCL – Configurable Custom Logic
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1407