Datasheet

Gated D-Latch (DLATCH)
When the DLATCH is selected, the D-input is driven by the even LUT output (LUT0 and LUT2), and the
G-input is driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 41-14.
Figure 41-16. D-Latch
D
Q
G
OUT
even LUT
odd LUT
When the even LUT is disabled (LUTCTRL0.ENABLE=0 /
LUTCTRL2.ENABLE=0), the latch output will be cleared. The G-input is forced enabled for one more APB
clock cycle, and the D-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in
Table 41-4.
Table 41-4. D-Latch Characteristics
G D OUT
0 X Hold state (no change)
1 0 Clear
1 1 Set
RS Latch (RS)
When this configuration is selected, the S-input is driven by the even LUT output (LUT0 and LUT2), and
the R-input is driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 41-17.
Figure 41-17. RS-Latch
S
Q
R
OUT
even LUT
odd LUT
When the even LUT is disabled LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the latch output will be
cleared. The R-input is forced enabled for one more APB clock cycle and S-input to zero. In all other
cases, the latch output (OUT) is refreshed as shown in Table 41-5.
Table 41-5. RS-Latch Characteristics
S R OUT
0 0 Hold state (no change)
0 1 Clear
1 0 Set
1 1 Forbidden state
41.6.3 Events
The CCL can generate the following output events:
• OUTx: Lookup Table Output Value
Writing a '1' to the LUT Control Event Output Enable bit (LUTCTRL.LUTEO) enables the corresponding
output event. Writing a '0' to this bit disables the corresponding output event.
SAM D5x/E5x Family Data Sheet
CCL – Configurable Custom Logic
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1405