Datasheet

Table Of Contents

41.6.2.5 Filter

By default, the LUT output is a combinatorial function of the LUT inputs. This may cause some short

glitches when the inputs change value. These glitches can be removed by clocking through filters, if

demanded by application needs.

The Filter Selection bits in LUT Control register (LUTCTRLx.FILTSEL) define the synchronizer or digital

filter options. When a filter is enabled, the OUT output will be delayed by two to five GCLK cycles. One

APB clock after the corresponding LUT is disabled, all internal filter logic is cleared.

Note: Events used as LUT input will also be filtered, if the filter is enabled.

Figure 41-12. Filter

FILTSEL

OUT

Input

GCLK_CCL

CLR

41.6.2.6 Edge Detector

The edge detector can be used to generate a pulse when detecting a rising edge on its input. To detect a

falling edge, the TRUTH table should be inverted.

The edge detector is enabled by writing '1' to the Edge Selection bit in LUT Control register

(LUTCTRLx.EDGESEL). In order to avoid unpredictable behavior, either the filter or synchronizer must be

enabled.

Edge detection is disabled by writing a '0' to LUTCTRLx.EDGESEL. After disabling a LUT, the

corresponding internal Edge Detector logic is cleared one APB clock cycle later.

Figure 41-13. Edge Detector

41.6.2.7 Sequential Logic

Each LUT pair can be connected to the internal sequential logic which can be configured to work as D flip

flop, JK flip flop, gated D-latch or RS-latch by writing the Sequential Selection bits on the corresponding

Sequential Control x register (SEQCTRLx.SEQSEL). Before using sequential logic, the GCLK_CCL clock

and optionally each LUT filter or edge detector must be enabled.

Note: While configuring the sequential logic, the even LUT must be disabled. When configured the even

LUT must be enabled.

SAM D5x/E5x Family Data Sheet

CCL – Configurable Custom Logic

Datasheet

DS60001507E-page 1403