Datasheet

41.5.2 Power Management
This peripheral can continue to operate in any Sleep mode where its source clock is running. Events
connected to the event system can trigger other operations in the system without exiting Sleep modes.
Related Links
18. PM – Power Manager
41.5.3 Clocks
The CCL bus clock (CLK_CCL_APB) can be enabled and disabled in the Main Clock module, MCLK (see
MCLK - Main Clock), and the default state of CLK_CCL_APB can be found in Peripheral Clock Masking.
A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and
enabled in the Generic Clock Controller (GCLK) before using input events, filter, edge detection or
sequential logic. GCLK_CCL is required when input events, a filter, an edge detector, or a sequential sub-
module is enabled. Refer to GCLK - Generic Clock Controller for details.
This generic clock is asynchronous to the user interface clock (CLK_CCL_APB).
Related Links
15. MCLK – Main Clock
15.6.2.6 Peripheral Clock Masking
14. GCLK - Generic Clock Controller
41.5.4 DMA
Not applicable.
41.5.5 Interrupts
Not applicable.
41.5.6 Events
The CCL can use events from other peripherals and generate events that can be used by other
peripherals. For this feature to function, the events have to be configured properly. Refer to the Related
Links below for more information about the event users and event generators.
Related Links
31. EVSYS – Event System
41.5.7 Debug Operation
When the CPU is halted in Debug mode the CCL continues normal operation. However, the CCL cannot
be halted when the CPU is halted in Debug mode. If the CCL is configured in a way that requires it to be
periodically serviced by the CPU, improper operation or data loss may result during debugging.
41.5.8 Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller
(PAC). Refer to PAC - Peripheral Access Controller for details.
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write
Protection" property in each individual register description.
PAC write protection does not apply to accesses through an external debugger.
Related Links
27. PAC - Peripheral Access Controller
SAM D5x/E5x Family Data Sheet
CCL – Configurable Custom Logic
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1395