Datasheet

40.8.37 e.MMC Control 1 Register
Name: MC1R
Offset: 0x204
Reset: 0x00
Property: R/W
Bit 7 6 5 4 3 2 1 0
FCD RSTN BOOTA OPD DDR CMDTYP[1:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – FCD e.MMC Force Card Detect
When using e.MMC, the user can set this bit to 1 to bypass the card detection procedure using the CD
signal.
Value Name Description
0
DISABLED e.MMC Forced Card Detect is disabled. The CD signal is used and debounce
timing is applied.
1
ENABLED e.MMC Forced Card Detect is enabled.
Bit 6 – RSTN e.MMC Reset Signal
This bit controls the e.MMC reset signal.
Value Description
0
Reset signal is inactive.
1
Reset signal is active.
Bit 5 – BOOTA e.MMC Boot Acknowledge Enable
This bit must be set according to the value of BOOT_ACK in the Extended CSD Register (refer to
“Embedded MultiMedia Card (e.MMC) Electrical Standard 4.51” ).
When this bit is set to 1, the peripheral waits for boot acknowledge pattern from the e.MMC before
receiving boot data.
If the boot acknowledge pattern is wrong, the BOOTAE status flag rises in EISTR if BOOTAE is set in
EISTER. An interrupt is generated if BOOTAE is set in EISIER.
If the no boot acknowledge pattern is received, the DATTEO status flag rises in EISTR if DATTEO is set
in EISTER. An interrupt is generated if DATTEO is set in EISIER.
Bit 4 – OPD e.MMC Open Drain Mode
This bit sets the command line in open drain.
Value Description
0
The command line is in push-pull.
1
The command line is in open drain.
Bit 3 – DDR e.MMC HSDDR Mode
This bit selects the High Speed DDR mode.
Value Description
0
High Speed DDR is not selected.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1386