Datasheet

tuning sequence in a short time. Changing this bit is not allowed while the peripheral is receiving a
response or a read data block. Refer to Figure 2.29 in the “SD Host Controller Simplified Specification
V3.00” .
Value Description
0
The fixed clock is used to sample data.
1
The tuned clock is used to sample data.
Bit 6 – EXTUN Execute Tuning
This bit is set to 1 to start the tuning procedure and is automatically cleared when the tuning procedure is
completed. The result of tuning is indicated to Sampling Clock Select (SCLKSEL). The tuning procedure
is aborted by writing 0. Refer to Figure 2.29 in the “SD Host Controller Simplified Specification V3.00” .
Value Description
0
Not tuned or tuning completed
1
Execute tuning
Bits 5:4 – DRVSEL[1:0] Driver Strength Select
The peripheral output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not
effective. This field can be set according to the Driver Type A, C and D support bits in CA1R.
This field depends on setting of Preset Value Enable (PVALEN):
• PVALEN=0 - This field is set by the user.
• PVALEN=1 - This field is automatically set by a value specified in one of the PVRx.
Value Name Description
0
TYPEB Driver Type B is selected (Default)
1
TYPEA Driver Type A is selected
2
TYPEC Driver Type C is selected
3
TYPED Driver Type D is selected
Bit 3 – VS18EN 1.8V Signaling Enable
This bit controls the voltage regulator for the I/O cell. 3.3V is supplied to the card regardless of the
signaling voltage.
Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. The 1.8V regulator output
must be stable within 5 ms.
Clearing this bit from 1 to 0 starts changing the signal voltage from 1.8V to 3.3V. The 3.3V regulator
output must be stable within 5ms.
The user can set this bit to 1 when the peripheral supports 1.8V signaling (one of the support bits is set to
1: SDR50SUP, SDR104SUP or DDR50SUP in CA1R) and the card or device supports UHS-I (S18A = 1.
Refer to “Bus Switch Voltage Switch Sequence in the “Physical Layer Simplified Specification V3.01” ).
Value Description
0
3.3V signaling
1
1.8V signaling
Bits 2:0 – UHSMS[2:0] UHS Mode Select
This field is used to select one of the UHS-I modes and is effective when 1.8V Signal Enable (VS18EN) is
set to 1.
If Preset Value Enable is set to 1, the peripheral sets SDCLK Frequency Select (SDCLKFSEL), Clock
Generator Select (CLKGSEL) in CCR and Driver Strength Select (DRVSEL) according to PVR. In this
case, one of the preset value registers is selected by this field. The user needs to reset SD Clock Enable
(SDCLKEN) before changing this field to avoid generating a clock glitch. After setting this field, the user
sets SDCLKEN to 1 again.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1368