Datasheet

40.8.24 Host Control 2 Register: e.MMC
Name: HC2R - EMMC
Offset: 0x3E
Reset: 0x0000
Property: -
Note: The content of the HC2R register is depending on the mode. This description is for e.MMC mode.
For SD/SDIO mode, see 40.8.25 HC2R - DEFAULT.
Bit 15 14 13 12 11 10 9 8
PVALEN
Access
R/W
Reset 0
Bit 7 6 5 4 3 2 1 0
SCLKSEL EXTUN DRVSEL[1:0] HS200EN[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 – PVALEN Preset Value Enable
As the operating SDCLK frequency depends on the system implementation, it is difficult to determine
these parameters in the standard host driver. When Preset Value Enable (PVALEN) is set to 1, automatic
SDCLK frequency generationis performed without considering system-specific conditions. This bit
enables the functions defined in PVR.
If this bit is written to 0, the Clock Generator Select bit (CCR.CLKGSEL) and the SDCLK Frequency
Select bit (CCR.SDCLKFSEL) in the Clock Control Register (CCR) are selected by the user.
If this bit is set to 1, CCR.SDCLKFSEL and .CLKGSEL and HC2R.DRVSEL are set by the peripheral as
specified in the Preset Value Register (PVR).
Value Description
0
CCR.SDCLK, CCR.SDCLKFSEL controlled by the user.
1
Automatic selection by Preset Value is enabled.
Bit 7 – SCLKSEL Sampling Clock Select
The peripheral uses this bit to select the sampling clock to receive CMD and DAT.
This bit is set by the tuning procedure and is valid after completion of tuning (when EXTUN is cleared).
Setting 1 means that tuning is completed successfully and setting 0 means that tuning has failed.
Writing 1 to this bit is meaningless and ignored. A tuning circuit is reset by writing to 0. This bit can be
cleared by setting EXTUN to 1. Once the tuning circuit is reset, it takes time to complete a tuning
sequence. Therefore, the user should keep this bit to 1 to perform a re-tuning sequence to complete a re-
tuning sequence in a short time. Changing this bit is not allowed while the peripheral is receiving a
response or a read data block. Refer to Figure 2.29 in the “SD Host Controller Simplified Specification
V3.00” .
Value Description
0
The fixed clock is used to sample data.
1
The tuned clock is used to sample data.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1365