Datasheet
Table Of Contents
- Features
- Table of Contents
- 1. Configuration Summary
- 2. Ordering Information
- 3. Block Diagram
- 4. Pinout
- 5. Signal Descriptions List
- 6. I/O Multiplexing and Considerations
- 6.1. Multiplexed Signals
- 6.2. Other Functions
- 7. Power Supply and Start-Up Considerations
- 8. Product Memory Mapping Overview
- 9. Memories
- 10. Processor and Architecture
- 11. CMCC - Cortex M Cache Controller
- 11.1. Overview
- 11.2. Features
- 11.3. Block Diagram
- 11.4. Signal Description
- 11.5. Product Dependencies
- 11.6. Functional Description
- 11.7. DEBUG Mode
- 11.8. RAM Properties
- 11.9. Register Summary
- 11.10. Register Description
- 12. DSU - Device Service Unit
- 12.1. Overview
- 12.2. Features
- 12.3. Block Diagram
- 12.4. Signal Description
- 12.5. Product Dependencies
- 12.6. Debug Operation
- 12.7. Chip Erase
- 12.8. Programming
- 12.9. Intellectual Property Protection
- 12.10. Device Identification
- 12.11. Functional Description
- 12.11.1. Principle of Operation
- 12.11.2. Basic Operation
- 12.11.3. 32-bit Cyclic Redundancy Check CRC32
- 12.11.4. Debug Communication Channels
- 12.11.5. Debug Communication Channels DMA connection
- 12.11.6. Testing of On-Board Memories MBIST
- 12.11.7. System Services Availability when Accessed Externally and Device is Protected
- 12.12. Register Summary
- 12.13. Register Description
- 12.13.1. Control
- 12.13.2. Status A
- 12.13.3. Status B
- 12.13.4. Address
- 12.13.5. Length
- 12.13.6. Data
- 12.13.7. Debug Communication Channel x
- 12.13.8. Device Identification
- 12.13.9. Configuration
- 12.13.10. Device Configuration
- 12.13.11. CoreSight ROM Table Entry x
- 12.13.12. CoreSight ROM Table End
- 12.13.13. CoreSight ROM Table Memory Type
- 12.13.14. Peripheral Identification 4
- 12.13.15. Peripheral Identification 7
- 12.13.16. Peripheral Identification 6
- 12.13.17. Peripheral Identification 5
- 12.13.18. Peripheral Identification 0
- 12.13.19. Peripheral Identification 1
- 12.13.20. Peripheral Identification 2
- 12.13.21. Peripheral Identification 3
- 12.13.22. Component Identification 0
- 12.13.23. Component Identification 1
- 12.13.24. Component Identification 2
- 12.13.25. Component Identification 3
- 13. Clock System
- 14. GCLK - Generic Clock Controller
- 14.1. Overview
- 14.2. Features
- 14.3. Block Diagram
- 14.4. Signal Description
- 14.5. Product Dependencies
- 14.6. Functional Description
- 14.7. Register Summary
- 14.8. Register Description
- 15. MCLK – Main Clock
- 15.1. Overview
- 15.2. Features
- 15.3. Block Diagram
- 15.4. Signal Description
- 15.5. Product Dependencies
- 15.6. Functional Description
- 15.7. Register Summary
- 15.8. Register Description
- 16. RSTC – Reset Controller
- 17. RAMECC – RAM Error Correction Code (ECC)
- 18. PM – Power Manager
- 18.1. Overview
- 18.2. Features
- 18.3. Block Diagram
- 18.4. Signal Description
- 18.5. Product Dependencies
- 18.6. Functional Description
- 18.6.1. Terminology
- 18.6.2. Principle of Operation
- 18.6.3. Basic Operation
- 18.6.4. Advanced Features
- 18.6.5. DMA Operation
- 18.6.6. Interrupts
- 18.6.7. Events
- 18.6.8. Sleep Mode Operation
- 18.7. Register Summary
- 18.8. Register Description
- 19. SUPC – Supply Controller
- 19.1. Overview
- 19.2. Features
- 19.3. Block Diagram
- 19.4. Signal Description
- 19.5. Product Dependencies
- 19.6. Functional Description
- 19.6.1. Voltage Regulator System Operation
- 19.6.2. Voltage Reference System Operation
- 19.6.3. Battery Backup Power Switch
- 19.6.4. Output Pins
- 19.6.5. Brown-Out Detectors
- 19.6.6. Interrupts
- 19.6.7. Synchronization
- 19.7. Register Summary
- 19.8. Register Description
- 19.8.1. Interrupt Enable Clear
- 19.8.2. Interrupt Enable Set
- 19.8.3. Interrupt Flag Status and Clear
- 19.8.4. Status
- 19.8.5. 3.3V Brown-Out Detector (BOD33) Control
- 19.8.6. Voltage Regulator System (VREG) Control
- 19.8.7. Voltage References System (VREF) Control
- 19.8.8. Battery Backup Power Switch (BBPS) Control
- 19.8.9. Backup Output (BKOUT) Control
- 19.8.10. Backup Input (BKIN) Value
- 20. WDT – Watchdog Timer
- 20.1. Overview
- 20.2. Features
- 20.3. Block Diagram
- 20.4. Signal Description
- 20.5. Product Dependencies
- 20.6. Functional Description
- 20.7. Register Summary
- 20.8. Register Description
- 21. RTC – Real-Time Counter
- 21.1. Overview
- 21.2. Features
- 21.3. Block Diagram
- 21.4. Signal Description
- 21.5. Product Dependencies
- 21.6. Functional Description
- 21.7. Register Summary - Mode 0 - 32-Bit Counter
- 21.8. Register Description - Mode 0 - 32-Bit Counter
- 21.8.1. Control A in COUNT32 mode (CTRLA.MODE=0)
- 21.8.2. Control B in COUNT32 mode (CTRLA.MODE=0)
- 21.8.3. Event Control in COUNT32 mode (CTRLA.MODE=0)
- 21.8.4. Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0)
- 21.8.5. Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0)
- 21.8.6. Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0)
- 21.8.7. Debug Control
- 21.8.8. Synchronization Busy in COUNT32 mode (CTRLA.MODE=0)
- 21.8.9. Frequency Correction
- 21.8.10. Counter Value in COUNT32 mode (CTRLA.MODE=0)
- 21.8.11. Compare n Value in COUNT32 mode (CTRLA.MODE=0)
- 21.8.12. General Purpose n
- 21.8.13. Tamper Control
- 21.8.14. Timestamp
- 21.8.15. Tamper ID
- 21.8.16. Backup n
- 21.9. Register Summary - Mode 1 - 16-Bit Counter
- 21.10. Register Description - Mode 1 - 16-Bit Counter
- 21.10.1. Control A in COUNT16 mode (CTRLA.MODE=1)
- 21.10.2. Control B in COUNT16 mode (CTRLA.MODE=1)
- 21.10.3. Event Control in COUNT16 mode (CTRLA.MODE=1)
- 21.10.4. Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1)
- 21.10.5. Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1)
- 21.10.6. Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1)
- 21.10.7. Debug Control
- 21.10.8. Synchronization Busy in COUNT16 mode (CTRLA.MODE=1)
- 21.10.9. Frequency Correction
- 21.10.10. Counter Value in COUNT16 mode (CTRLA.MODE=1)
- 21.10.11. Counter Period in COUNT16 mode (CTRLA.MODE=1)
- 21.10.12. Compare n Value in COUNT16 mode (CTRLA.MODE=1)
- 21.10.13. General Purpose n
- 21.10.14. Tamper Control
- 21.10.15. Timestamp
- 21.10.16. Tamper ID
- 21.10.17. Backup n
- 21.11. Register Summary - Mode 2 - Clock/Calendar
- 21.12. Register Description - Mode 2 - Clock/Calendar
- 21.12.1. Control A in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.2. Control B in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.3. Event Control in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.4. Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.5. Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.6. Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.7. Debug Control
- 21.12.8. Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.9. Frequency Correction
- 21.12.10. Clock Value in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.11. Alarm n Value in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.12. Alarm n Mask in Clock/Calendar mode (CTRLA.MODE=2)
- 21.12.13. General Purpose n
- 21.12.14. Tamper Control
- 21.12.15. Timestamp Value
- 21.12.16. Tamper ID
- 21.12.17. Backup n
- 22. DMAC – Direct Memory Access Controller
- 22.1. Overview
- 22.2. Features
- 22.3. Block Diagram
- 22.4. Signal Description
- 22.5. Product Dependencies
- 22.6. Functional Description
- 22.6.1. Principle of Operation
- 22.6.2. Basic Operation
- 22.6.3. Additional Features
- 22.6.3.1. Linked Descriptors
- 22.6.3.2. Transfer Quality of Service
- 22.6.3.3. Channel Suspend
- 22.6.3.4. Channel Resume and Next Suspend Skip
- 22.6.3.5. Event Input Actions
- 22.6.3.6. Event Output Selection
- 22.6.3.7. Aborting Transfers
- 22.6.3.8. CRC Operation
- 22.6.3.9. Memory CRC Generation
- 22.6.3.10. Memory CRC Monitor
- 22.6.4. DMA Operation
- 22.6.5. Interrupts
- 22.6.6. Events
- 22.6.7. Sleep Mode Operation
- 22.6.8. Synchronization
- 22.7. Register Summary
- 22.8. Register Description
- 22.8.1. Control
- 22.8.2. CRC Control
- 22.8.3. CRC Data Input
- 22.8.4. CRC Checksum
- 22.8.5. CRC Status
- 22.8.6. Debug Control
- 22.8.7. Software Trigger Control
- 22.8.8. Priority Control 0
- 22.8.9. Interrupt Pending
- 22.8.10. Interrupt Status
- 22.8.11. Busy Channels
- 22.8.12. Pending Channels
- 22.8.13. Active Channel and Levels
- 22.8.14. Descriptor Memory Section Base Address
- 22.8.15. Write-Back Memory Section Base Address
- 22.8.16. Channel Control A
- 22.8.17. Channel Control B
- 22.8.18. Channel Priority Level
- 22.8.19. Channel Event Control
- 22.8.20. Channel Interrupt Enable Clear
- 22.8.21. Channel Interrupt Enable Set
- 22.8.22. Channel Interrupt Flag Status and Clear
- 22.8.23. Channel Status
- 22.9. Register Summary - SRAM
- 22.10. Register Description - SRAM
- 23. EIC – External Interrupt Controller
- 23.1. Overview
- 23.2. Features
- 23.3. Block Diagram
- 23.4. Signal Description
- 23.5. Product Dependencies
- 23.6. Functional Description
- 23.7. Register Summary
- 23.8. Register Description
- 23.8.1. Control A
- 23.8.2. Non-Maskable Interrupt Control
- 23.8.3. Non-Maskable Interrupt Flag Status and Clear
- 23.8.4. Synchronization Busy
- 23.8.5. Event Control
- 23.8.6. Interrupt Enable Clear
- 23.8.7. Interrupt Enable Set
- 23.8.8. Interrupt Flag Status and Clear
- 23.8.9. External Interrupt Asynchronous Mode
- 23.8.10. External Interrupt Sense Configuration n
- 23.8.11. Debouncer Enable
- 23.8.12. Debouncer Prescaler
- 23.8.13. Pin State
- 24. GMAC - Ethernet MAC
- 24.1. Description
- 24.2. Features
- 24.3. Block Diagram
- 24.4. Signal Description
- 24.5. Product Dependencies
- 24.6. Functional Description
- 24.6.1. Media Access Controller
- 24.6.2. IEEE 1588 Time Stamp Unit
- 24.6.3. AHB Direct Memory Access Interface
- 24.6.4. MAC Transmit Block
- 24.6.5. MAC Receive Block
- 24.6.6. Checksum Offload for IP, TCP and UDP
- 24.6.7. MAC Filtering Block
- 24.6.8. Broadcast Address
- 24.6.9. Hash Addressing
- 24.6.10. Copy all Frames (Promiscuous Mode)
- 24.6.11. Disable Copy of Pause Frames
- 24.6.12. VLAN Support
- 24.6.13. Wake on LAN Support
- 24.6.14. IEEE 1588 Support
- 24.6.15. Time Stamp Unit
- 24.6.16. MAC 802.3 Pause Frame Support
- 24.6.17. Energy Efficient Ethernet Support
- 24.6.18. 802.1Qav Support - Credit-based Shaping
- 24.6.19. PHY Interface
- 24.6.20. 10/100 Operation
- 24.6.21. Jumbo Frames
- 24.7. Programming Interface
- 24.8. Register Summary
- 24.9. Register Description
- 24.9.1. GMAC Network Control Register
- 24.9.2. GMAC Network Configuration Register
- 24.9.3. GMAC Network Status Register
- 24.9.4. GMAC User Register
- 24.9.5. GMAC DMA Configuration Register
- 24.9.6. GMAC Transmit Status Register
- 24.9.7. GMAC Receive Buffer Queue Base Address Register
- 24.9.8. GMAC Transmit Buffer Queue Base Address Register
- 24.9.9. GMAC Receive Status Register
- 24.9.10. GMAC Interrupt Status Register
- 24.9.11. GMAC Interrupt Enable Register
- 24.9.12. GMAC Interrupt Disable Register
- 24.9.13. GMAC Interrupt Mask Register
- 24.9.14. GMAC PHY Maintenance Register
- 24.9.15. GMAC Receive Pause Quantum Register
- 24.9.16. GMAC Transmit Pause Quantum Register
- 24.9.17. GMAC TX Partial Store and Forward Register
- 24.9.18. GMAC RX Partial Store and Forward Register
- 24.9.19. GMAC RX Jumbo Frame Max Length Register
- 24.9.20. GMAC Hash Register Bottom
- 24.9.21. GMAC Hash Register Top
- 24.9.22. GMAC Specific Address n Bottom Register
- 24.9.23. GMAC Specific Address n Top Register
- 24.9.24. GMAC Type ID Match n Register
- 24.9.25. GMAC Wake on LAN Register
- 24.9.26. GMAC IPG Stretch Register
- 24.9.27. GMAC Stacked VLAN Register
- 24.9.28. GMAC Specific Address 1 Mask Bottom
- 24.9.29. GMAC Specific Address Mask 1 Top
- 24.9.30. GMAC 1588 Timer Nanosecond Comparison Register
- 24.9.31. GMAC 1588 Timer Second Comparison Low Register
- 24.9.32. GMAC 1588 Timer Second Comparison High Register
- 24.9.33. GMAC PTP Event Frame Transmitted Seconds High Register
- 24.9.34. GMAC PTP Event Frame Received Seconds High Register
- 24.9.35. GMAC PTP Peer Event Frame Transmitted Seconds High Register
- 24.9.36. GMAC PTP Peer Event Frame Received Seconds High Register
- 24.9.37. GMAC Octets Transmitted Low Register
- 24.9.38. GMAC Octets Transmitted High Register
- 24.9.39. GMAC Frames Transmitted
- 24.9.40. GMAC Broadcast Frames Transmitted Register
- 24.9.41. GMAC Multicast Frames Transmitted Register
- 24.9.42. GMAC Pause Frames Transmitted Register
- 24.9.43. GMAC 64 Byte Frames Transmitted Register
- 24.9.44. GMAC 65 to 127 Byte Frames Transmitted Register
- 24.9.45. GMAC 128 to 255 Byte Frames Transmitted Register
- 24.9.46. GMAC 256 to 511 Byte Frames Transmitted Register
- 24.9.47. GMAC 512 to 1023 Byte Frames Transmitted Register
- 24.9.48. GMAC 1024 to 1518 Byte Frames Transmitted Register
- 24.9.49. GMAC Greater Than 1518 Byte Frames Transmitted Register
- 24.9.50. GMAC Transmit Underruns Register
- 24.9.51. GMAC Single Collision Frames Register
- 24.9.52. GMAC Multiple Collision Frames Register
- 24.9.53. GMAC Excessive Collisions Register
- 24.9.54. GMAC Late Collisions Register
- 24.9.55. GMAC Deferred Transmission Frames Register
- 24.9.56. GMAC Carrier Sense Errors Register
- 24.9.57. GMAC Octets Received Low Register
- 24.9.58. GMAC Octets Received High Register
- 24.9.59. GMAC Frames Received Register
- 24.9.60. GMAC Broadcast Frames Received Register
- 24.9.61. GMAC Multicast Frames Received Register
- 24.9.62. GMAC Pause Frames Received Register
- 24.9.63. GMAC 64 Byte Frames Received Register
- 24.9.64. GMAC 65 to 127 Byte Frames Received Register
- 24.9.65. GMAC 128 to 255 Byte Frames Received Register
- 24.9.66. GMAC 256 to 511 Byte Frames Received Register
- 24.9.67. GMAC 512 to 1023 Byte Frames Received Register
- 24.9.68. GMAC 1024 to 1518 Byte Frames Received Register
- 24.9.69. GMAC 1519 to Maximum Byte Frames Received Register
- 24.9.70. GMAC Undersized Frames Received Register
- 24.9.71. GMAC Oversized Frames Received Register
- 24.9.72. GMAC Jabbers Received Register
- 24.9.73. GMAC Frame Check Sequence Errors Register
- 24.9.74. GMAC Length Field Frame Errors Register
- 24.9.75. GMAC Receive Symbol Errors Register
- 24.9.76. GMAC Alignment Errors Register
- 24.9.77. GMAC Receive Resource Errors Register
- 24.9.78. GMAC Receive Overruns Register
- 24.9.79. GMAC IP Header Checksum Errors Register
- 24.9.80. GMAC TCP Checksum Errors Register
- 24.9.81. GMAC UDP Checksum Errors Register
- 24.9.82. GMAC 1588 Timer Increment Sub-nanoseconds Register
- 24.9.83. GMAC 1588 Timer Seconds High Register
- 24.9.84. GMAC 1588 Timer Seconds Low Register
- 24.9.85. 1588 Timer Sync Strobe Seconds [31:0] Register
- 24.9.86. GMAC 1588 Timer Sync Strobe Nanoseconds Register
- 24.9.87. GMAC 1588 Timer Nanoseconds Register
- 24.9.88. GMAC 1588 Timer Adjust Register
- 24.9.89. GMAC IEEE 1588 Timer Increment Register
- 24.9.90. GMAC PTP Event Frame Transmitted Seconds Low Register
- 24.9.91. GMAC PTP Event Frame Transmitted Nanoseconds Register
- 24.9.92. GMAC PTP Event Frame Received Seconds Low Register
- 24.9.93. GMAC PTP Event Frame Received Nanoseconds Register
- 24.9.94. GMAC PTP Peer Event Frame Transmitted Seconds Low Register
- 24.9.95. GMAC PTP Peer Event Frame Transmitted Nanoseconds Register
- 24.9.96. GMAC PTP Peer Event Frame Received Seconds Low Register
- 24.9.97. GMAC PTP Peer Event Frame Received Nanoseconds Register
- 24.9.98. Received LPI Transitions
- 24.9.99. Received LPI Time
- 24.9.100. Transmit LPI Transitions
- 24.9.101. Transmit LPI Time
- 25. NVMCTRL – Nonvolatile Memory Controller
- 25.1. Overview
- 25.2. Features
- 25.3. Block Diagram
- 25.4. Signal Description
- 25.5. Product Dependencies
- 25.6. Functional Description
- 25.6.1. Principle of Operation
- 25.6.2. Memory Organization
- 25.6.3. Memory Bank Swapping
- 25.6.4. AHBMUX Arbitration
- 25.6.5. Region Lock Bits
- 25.6.6. Command and Data Interface
- 25.6.7. Safe Flash Update Using Dual Banks
- 25.6.8. SmartEEPROM
- 25.6.9. NVM User Configuration
- 25.6.10. Security Bit
- 25.6.11. Line Cache
- 25.6.12. Error Correction Code (ECC)
- 25.6.13. Reset During Operation
- 25.6.14. Chip Erase
- 25.7. Register Summary
- 25.8. Register Description
- 25.8.1. Control A
- 25.8.2. Control B
- 25.8.3. NVM Parameter
- 25.8.4. Interrupt Enable Clear
- 25.8.5. Interrupt Enable Set
- 25.8.6. Interrupt Flag Status and Clear
- 25.8.7. Status
- 25.8.8. Address
- 25.8.9. Lock Section
- 25.8.10. Page Buffer Load Data x
- 25.8.11. ECC Error Status
- 25.8.12. Debug Control
- 25.8.13. SmartEEPROM Configuration
- 25.8.14. SmartEEPROM Status
- 26. ICM - Integrity Check Monitor
- 26.1. Overview
- 26.2. Features
- 26.3. Block Diagram
- 26.4. Signal Description
- 26.5. Product Dependencies
- 26.6. Functional Description
- 26.7. Register Summary - ICM
- 26.8. Register Description
- 26.8.1. Configuration Register
- 26.8.2. Control Register
- 26.8.3. Status Register
- 26.8.4. Interrupt Enable Register
- 26.8.5. Interrupt Disable Register
- 26.8.6. Interrupt Mask Register
- 26.8.7. Interrupt Status Register
- 26.8.8. Undefined Access Status Register
- 26.8.9. Descriptor Area Start Address Register
- 26.8.10. Hash Area Start Address Register
- 26.8.11. User Initial Hash Value Register
- 27. PAC - Peripheral Access Controller
- 27.1. Overview
- 27.2. Features
- 27.3. Block Diagram
- 27.4. Product Dependencies
- 27.5. Functional Description
- 27.6. Register Summary
- 27.7. Register Description
- 27.7.1. Write Control
- 27.7.2. Event Control
- 27.7.3. Interrupt Enable Clear
- 27.7.4. Interrupt Enable Set
- 27.7.5. Bridge Interrupt Flag Status
- 27.7.6. Peripheral Interrupt Flag Status - Bridge A
- 27.7.7. Peripheral Interrupt Flag Status - Bridge B
- 27.7.8. Peripheral Interrupt Flag Status - Bridge C
- 27.7.9. Peripheral Interrupt Flag Status - Bridge D
- 27.7.10. Peripheral Write Protection Status A
- 27.7.11. Peripheral Write Protection Status - Bridge B
- 27.7.12. Peripheral Write Protection Status - Bridge C
- 27.7.13. Peripheral Write Protection Status - Bridge D
- 28. OSCCTRL – Oscillators Controller
- 28.1. Overview
- 28.2. Features
- 28.3. Block Diagram
- 28.4. Signal Description
- 28.5. Product Dependencies
- 28.6. Functional Description
- 28.6.1. Principle of Operation
- 28.6.2. External Multipurpose Crystal Oscillator (XOSCn) Operation
- 28.6.3. Clock Failure Detection Operation
- 28.6.4. Digital Frequency Locked Loop (DFLL48M) Operation
- 28.6.5. Digital Phase Locked Loop (DPLL) Operation
- 28.6.6. DMA Operation
- 28.6.7. Interrupts
- 28.6.8. Events
- 28.6.9. Synchronization
- 28.7. Register Summary
- 28.8. Register Description
- 28.8.1. Event Control
- 28.8.2. Interrupt Enable Clear
- 28.8.3. Interrupt Enable Set
- 28.8.4. Interrupt Flag Status and Clear
- 28.8.5. Status
- 28.8.6. External Multipurpose Crystal Oscillator Control
- 28.8.7. DFLL48M Control A
- 28.8.8. DFLL48M Control B
- 28.8.9. DFLL48M Value
- 28.8.10. DFLL48M Multiplier
- 28.8.11. DFLL48M Synchronization
- 28.8.12. DPLL Control A
- 28.8.13. DPLL Ratio Control
- 28.8.14. DPLL Control B
- 28.8.15. DPLL Synchronization Busy
- 28.8.16. DPLL Status
- 29. OSC32KCTRL – 32KHz Oscillators Controller
- 29.1. Overview
- 29.2. Features
- 29.3. Block Diagram
- 29.4. Signal Description
- 29.5. Product Dependencies
- 29.6. Functional Description
- 29.6.1. Principle of Operation
- 29.6.2. 32 kHz External Crystal Oscillator (XOSC32K) Operation
- 29.6.3. Clock Failure Detection Operation
- 29.6.4. 32 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) Operation
- 29.6.5. Watchdog Timer Clock Selection
- 29.6.6. Real-Time Counter Clock Selection
- 29.6.7. Interrupts
- 29.6.8. Events
- 29.7. Register Summary
- 29.8. Register Description
- 29.8.1. Interrupt Enable Clear
- 29.8.2. Interrupt Enable Set
- 29.8.3. Interrupt Flag Status and Clear
- 29.8.4. Status
- 29.8.5. RTC Clock Selection Control
- 29.8.6. 32KHz External Crystal Oscillator (XOSC32K) Control
- 29.8.7. Clock Failure Detector Control
- 29.8.8. Event Control
- 29.8.9. 32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
- 30. FREQM – Frequency Meter
- 31. EVSYS – Event System
- 31.1. Overview
- 31.2. Features
- 31.3. Block Diagram
- 31.4. Product Dependencies
- 31.5. Functional Description
- 31.5.1. Principle of Operation
- 31.5.2. Basic Operation
- 31.5.2.1. Initialization
- 31.5.2.2. Enabling, Disabling, and Resetting
- 31.5.2.3. User Multiplexer Setup
- 31.5.2.4. Event System Channel
- 31.5.2.5. Event Generators
- 31.5.2.6. Channel Path
- 31.5.2.7. Edge Detection
- 31.5.2.8. Event Latency
- 31.5.2.9. The Overrun Channel n Interrupt
- 31.5.2.10. The Event Detected Channel n Interrupt
- 31.5.2.11. Channel Status
- 31.5.2.12. Software Event
- 31.5.2.13. Interrupt Status and Interrupts Arbitration
- 31.5.3. Interrupts
- 31.5.4. Sleep Mode Operation
- 31.6. Register Summary
- 31.7. Register Description
- 31.7.1. Control A
- 31.7.2. Software Event
- 31.7.3. Priority Control
- 31.7.4. Channel Pending Interrupt
- 31.7.5. Interrupt Status
- 31.7.6. Busy Channels
- 31.7.7. Ready Users
- 31.7.8. Channel n Control
- 31.7.9. Channel n Interrupt Enable Clear
- 31.7.10. Channel n Interrupt Enable Set
- 31.7.11. Channel n Interrupt Flag Status and Clear
- 31.7.12. Channel n Status
- 31.7.13. Event User m
- 32. PORT - I/O Pin Controller
- 32.1. Overview
- 32.2. Features
- 32.3. Block Diagram
- 32.4. Signal Description
- 32.5. Product Dependencies
- 32.6. Functional Description
- 32.7. Register Summary
- 32.8. Register Description
- 32.8.1. Data Direction
- 32.8.2. Data Direction Clear
- 32.8.3. Data Direction Set
- 32.8.4. Data Direction Toggle
- 32.8.5. Data Output Value
- 32.8.6. Data Output Value Clear
- 32.8.7. Data Output Value Set
- 32.8.8. Data Output Value Toggle
- 32.8.9. Data Input Value
- 32.8.10. Control
- 32.8.11. Write Configuration
- 32.8.12. Event Input Control
- 32.8.13. Peripheral Multiplexing n
- 32.8.14. Pin Configuration
- 33. SERCOM – Serial Communication Interface
- 33.1. Overview
- 33.2. Features
- 33.3. Block Diagram
- 33.4. Signal Description
- 33.5. Product Dependencies
- 33.6. Functional Description
- 34. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter
- 34.1. Overview
- 34.2. USART Features
- 34.3. Block Diagram
- 34.4. Signal Description
- 34.5. Product Dependencies
- 34.6. Functional Description
- 34.6.1. Principle of Operation
- 34.6.2. Basic Operation
- 34.6.3. Additional Features
- 34.6.3.1. Parity
- 34.6.3.2. Hardware Handshaking
- 34.6.3.3. IrDA Modulation and Demodulation
- 34.6.3.4. Break Character Detection and Auto-Baud/LIN Slave
- 34.6.3.5. LIN Master
- 34.6.3.6. RS485
- 34.6.3.7. ISO 7816 for Smart Card Interfacing
- 34.6.3.8. Collision Detection
- 34.6.3.9. Loop-Back Mode
- 34.6.3.10. Start-of-Frame Detection
- 34.6.3.11. Sample Adjustment
- 34.6.3.12. 32-bit Extension
- 34.6.4. DMA, Interrupts and Events
- 34.6.5. Sleep Mode Operation
- 34.6.6. Synchronization
- 34.7. Register Summary
- 34.8. Register Description
- 34.8.1. Control A
- 34.8.2. Control B
- 34.8.3. Control C
- 34.8.4. Baud
- 34.8.5. Receive Pulse Length Register
- 34.8.6. Interrupt Enable Clear
- 34.8.7. Interrupt Enable Set
- 34.8.8. Interrupt Flag Status and Clear
- 34.8.9. Status
- 34.8.10. Synchronization Busy
- 34.8.11. Receive Error Count
- 34.8.12. Length
- 34.8.13. Data
- 34.8.14. Debug Control
- 35. SERCOM SPI – SERCOM Serial Peripheral Interface
- 35.1. Overview
- 35.2. Features
- 35.3. Block Diagram
- 35.4. Signal Description
- 35.5. Product Dependencies
- 35.6. Functional Description
- 35.7. Register Summary
- 35.8. Register Description
- 36. SERCOM I2C – Inter-Integrated Circuit
- 36.1. Overview
- 36.2. Features
- 36.3. Block Diagram
- 36.4. Signal Description
- 36.5. Product Dependencies
- 36.6. Functional Description
- 36.6.1. Principle of Operation
- 36.6.2. Basic Operation
- 36.6.2.1. Initialization
- 36.6.2.2. Enabling, Disabling, and Resetting
- 36.6.2.3. I2C Bus State Logic
- 36.6.2.4. I2C Master Operation
- 36.6.2.5. I2C Slave Operation
- 36.6.3. Additional Features
- 36.6.4. DMA, Interrupts and Events
- 36.6.5. Sleep Mode Operation
- 36.6.6. Synchronization
- 36.7. Register Summary - I2C Slave
- 36.8. Register Description - I2C Slave
- 36.9. Register Summary - I2C Master
- 36.10. Register Description - I2C Master
- 37. QSPI - Quad Serial Peripheral Interface
- 37.1. Overview
- 37.2. Features
- 37.3. Block Diagram
- 37.4. Signal Description
- 37.5. Product Dependencies
- 37.6. Functional Description
- 37.6.1. Principle of Operation
- 37.6.2. Basic Operation
- 37.6.3. Transfer Data Rate
- 37.6.4. Serial Clock Baudrate
- 37.6.5. Serial Clock Phase and Polarity
- 37.6.6. Transfer Delays
- 37.6.7. QSPI SPI Mode
- 37.6.8. QSPI Serial Memory Mode
- 37.6.9. Scrambling/Unscrambling Function
- 37.6.10. DMA Operation
- 37.6.11. Interrupts
- 37.7. Register Summary
- 37.8. Register Description
- 37.8.1. Control A
- 37.8.2. Control B
- 37.8.3. Baud Rate
- 37.8.4. Receive Data
- 37.8.5. Transmit Data
- 37.8.6. Interrupt Enable Clear
- 37.8.7. Interrupt Enable Set
- 37.8.8. Interrupt Flag Status and Clear
- 37.8.9. Status
- 37.8.10. Instruction Address
- 37.8.11. Instruction Code
- 37.8.12. Instruction Frame
- 37.8.13. Scrambling Mode
- 37.8.14. Scrambling Key
- 38. USB – Universal Serial Bus
- 38.1. Overview
- 38.2. Features
- 38.3. USB Block Diagram
- 38.4. Signal Description
- 38.5. Product Dependencies
- 38.6. Functional Description
- 38.6.1. USB General Operation
- 38.6.2. USB Device Operations
- 38.6.2.1. Initialization
- 38.6.2.2. Endpoint Configuration
- 38.6.2.3. Multi-Packet Transfers
- 38.6.2.4. USB Reset
- 38.6.2.5. Start-of-Frame
- 38.6.2.6. Management of SETUP Transactions
- 38.6.2.7. Management of OUT Transactions
- 38.6.2.8. Multi-Packet Transfers for OUT Endpoint
- 38.6.2.9. Management of IN Transactions
- 38.6.2.10. Multi-Packet Transfers for IN Endpoint
- 38.6.2.11. Ping-Pong Operation
- 38.6.2.12. Feedback Operation
- 38.6.2.13. Suspend State and Pad Behavior
- 38.6.2.14. Remote Wakeup
- 38.6.2.15. Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device
- 38.6.2.16. USB Device Interrupt
- 38.6.3. Host Operations
- 38.6.3.1. Device Detection and Disconnection
- 38.6.3.2. Host Terminology
- 38.6.3.3. USB Reset
- 38.6.3.4. Pipe Configuration
- 38.6.3.5. Pipe Activation
- 38.6.3.6. Pipe Address Setup
- 38.6.3.7. Suspend and Wakeup
- 38.6.3.8. Phase-locked SOFs
- 38.6.3.9. Management of Control Pipes
- 38.6.3.10. Management of IN Pipes
- 38.6.3.11. Management of OUT Pipes
- 38.6.3.12. Alternate Pipe
- 38.6.3.13. Data Flow Error
- 38.6.3.14. CRC Error
- 38.6.3.15. PERR Error
- 38.6.3.16. Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
- 38.6.3.17. Host Interrupt
- 38.7. Register Summary
- 38.8. Register Description
- 38.8.1. Communication Device Host Registers
- 38.8.2. Device Registers - Common
- 38.8.3. Device Registers - Endpoint
- 38.8.4. Device Registers - Endpoint RAM
- 38.8.5. Host Registers - Common
- 38.8.6. Host Registers - Pipe
- 38.8.6.1. Host Pipe n Configuration
- 38.8.6.2. Interval for the Bulk-Out/Ping Transaction
- 38.8.6.3. Pipe Status Clear n
- 38.8.6.4. Pipe Status Set Register n
- 38.8.6.5. Pipe Status Register n
- 38.8.6.6. Host Pipe Interrupt Flag Register
- 38.8.6.7. Host Pipe Interrupt Clear Register
- 38.8.6.8. Host Interrupt Pipe Set Register
- 38.8.7. Host Registers - Pipe RAM
- 39. CAN - Control Area Network
- 39.1. Overview
- 39.2. Features
- 39.3. Block Diagram
- 39.4. Signal Description
- 39.5. Product Dependencies
- 39.6. Functional Description
- 39.7. Register Summary
- 39.8. Register Description
- 39.8.1. Core Release
- 39.8.2. Endian
- 39.8.3. Message RAM Configuration
- 39.8.4. Data Bit Timing and Prescaler
- 39.8.5. Test
- 39.8.6. RAM Watchdog
- 39.8.7. CC Control
- 39.8.8. Nominal Bit Timing and Prescaler
- 39.8.9. Timestamp Counter Configuration
- 39.8.10. Timestamp Counter Value
- 39.8.11. Timeout Counter Configuration
- 39.8.12. Timeout Counter Value
- 39.8.13. Error Counter
- 39.8.14. Protocol Status
- 39.8.15. Transmitter Delay Compensation
- 39.8.16. Interrupt
- 39.8.17. Interrupt Enable
- 39.8.18. Interrupt Line Select
- 39.8.19. Interrupt Line Enable
- 39.8.20. Global Filter Configuration
- 39.8.21. Standard ID Filter Configuration
- 39.8.22. Extended ID Filter Configuration
- 39.8.23. Extended ID AND Mask
- 39.8.24. High Priority Message Status
- 39.8.25. New Data 1
- 39.8.26. New Data 2
- 39.8.27. Rx FIFO 0 Configuration
- 39.8.28. Rx FIFO 0 Status
- 39.8.29. Rx FIFO 0 Acknowledge
- 39.8.30. Rx Buffer Configuration
- 39.8.31. Rx FIFO 1 Configuration
- 39.8.32. Rx FIFO 1 Status
- 39.8.33. Rx FIFO 1 Acknowledge
- 39.8.34. Rx Buffer / FIFO Element Size Configuration
- 39.8.35. Tx Buffer Configuration
- 39.8.36. Tx FIFO/Queue Status
- 39.8.37. Tx Buffer Element Size Configuration
- 39.8.38. Tx Buffer Request Pending
- 39.8.39. Tx Buffer Add Request
- 39.8.40. Tx Buffer Cancellation Request
- 39.8.41. Tx Buffer Transmission Occurred
- 39.8.42. Tx Buffer Cancellation Finished
- 39.8.43. Tx Buffer Transmission Interrupt Enable
- 39.8.44. Tx Buffer Cancellation Finished Interrupt Enable
- 39.8.45. Tx Event FIFO Configuration
- 39.8.46. Tx Event FIFO Status
- 39.8.47. Tx Event FIFO Acknowledge
- 39.9. Message RAM
- 40. SD/MMC Host Controller (SDHC)
- 40.1. Overview
- 40.2. Features
- 40.3. Block Diagrams
- 40.4. Signal Description
- 40.5. Product Dependencies
- 40.6. Functional Description
- 40.7. Register Summary
- 40.8. Register Description
- 40.8.1. SDMA System Address / Argument 2 Register
- 40.8.2. Block Size Register
- 40.8.3. Block Count Register
- 40.8.4. Argument 1 Register
- 40.8.5. Transfer Mode Register
- 40.8.6. Command Register
- 40.8.7. Response Register n
- 40.8.8. Buffer Data Port Register
- 40.8.9. Present State Register
- 40.8.10. Host Control 1 Register
- 40.8.11. Power Control Register
- 40.8.12. Block Gap Control Register
- 40.8.13. Wakeup Control Register: SD/SDIO
- 40.8.14. Clock Control Register
- 40.8.15. Timeout Control Register
- 40.8.16. Software Reset Register
- 40.8.17. Normal Interrupt Status Register
- 40.8.18. Error Interrupt Status Register
- 40.8.19. Normal Interrupt Status Enable Register: e.MMC
- 40.8.20. Error Interrupt Status Enable Register
- 40.8.21. Normal Interrupt Signal Enable Register
- 40.8.22. Error Interrupt Signal Enable Register
- 40.8.23. Auto CMD Error Status Register
- 40.8.24. Host Control 2 Register: e.MMC
- 40.8.25. Host Control 2 Register: SD/SDIO
- 40.8.26. Capabilities 0 Register
- 40.8.27. Capabilities 1 Register
- 40.8.28. Maximum Current Capabilities Register
- 40.8.29. Force Event Register for Auto CMD Error Status
- 40.8.30. Force Event Register for Error Interrupt Status
- 40.8.31. ADMA Error Status Register
- 40.8.32. ADMA System Address Register
- 40.8.33. Preset Value Register
- 40.8.34. Slot Interrupt Status Register
- 40.8.35. Host Controller Version Register
- 40.8.36. Additional Present State Register
- 40.8.37. e.MMC Control 1 Register
- 40.8.38. e.MMC Control 2 Register
- 40.8.39. AHB Control Register
- 40.8.40. Clock Control 2 Register
- 40.8.41. Capabilities Control Register
- 40.8.42. Debug Register
- 41. CCL – Configurable Custom Logic
- 42. AES – Advanced Encryption Standard
- 42.1. Overview
- 42.2. Features
- 42.3. Block Diagram
- 42.4. Signal Description
- 42.5. Product Dependencies
- 42.6. Functional Description
- 42.7. Register Summary
- 42.8. Register Description
- 42.8.1. Control A
- 42.8.2. Control B
- 42.8.3. Interrupt Enable Clear
- 42.8.4. Interrupt Enable Set
- 42.8.5. Interrupt Flag Status and Clear
- 42.8.6. Data Buffer Pointer
- 42.8.7. Debug
- 42.8.8. Keyword
- 42.8.9. Data
- 42.8.10. Initialization Vector Register
- 42.8.11. Hash Key (GCM mode only)
- 42.8.12. Galois Hash (GCM mode only)
- 42.8.13. Galois Hash x (GCM mode only)
- 42.8.14. Random Seed
- 43. Public Key Cryptography Controller (PUKCC)
- 43.1. Overview
- 43.2. Product Dependencies
- 43.3. Functional Description
- 43.3.1. Public Key Cryptography Library (PUKCL) Application Programming Interface (API)
- 43.3.2. PUKCL Features
- 43.3.3. PUCKL Usage
- 43.3.4. Basic Arithmetic and Cryptographic Services
- 43.3.4.1. SelfTest
- 43.3.4.2. Clear Flags
- 43.3.4.3. Swap
- 43.3.4.4. Fill
- 43.3.4.5. Fast Copy/Clear
- 43.3.4.6. Conditional Copy/Clear
- 43.3.4.7. Small Multiply, Add, Subtract, Exclusive OR
- 43.3.4.8. Compare
- 43.3.4.9. Full Multiply
- 43.3.4.9.1. Purpose
- 43.3.4.9.2. How to Use the Service
- 43.3.4.9.3. Description
- 43.3.4.9.4. Parameters Definition
- 43.3.4.9.5. Available Options
- 43.3.4.9.6. Code Example
- 43.3.4.9.7. Important Considerations for Modular Reduction of a Fmult Computation Result
- 43.3.4.9.8. Constraints
- 43.3.4.9.9. Status Returned Values
- 43.3.4.10. Square
- 43.3.4.10.1. Purpose
- 43.3.4.10.2. How to Use the Service
- 43.3.4.10.3. Description
- 43.3.4.10.4. Parameters Definition
- 43.3.4.10.5. Available Options
- 43.3.4.10.6. Code Example
- 43.3.4.10.7. Important Considerations for Modular Reduction of a Square Computation
- 43.3.4.10.8. Constraints
- 43.3.4.10.9. Multiplication without Accumulation or Subtraction
- 43.3.4.10.10. Status Returned Values
- 43.3.4.11. Integral (Euclidean) Division
- 43.3.4.12. GCD, Modular Inverse
- 43.3.4.13. Get Random Number
- 43.3.4.13.1. Purpose
- 43.3.4.13.2. How to Use the Service
- 43.3.4.13.3. Description
- 43.3.4.13.4. Generation of a Random Number from the Deterministic RNG
- 43.3.4.13.5. Hardware RNG Parameters Definition
- 43.3.4.13.6. Deterministic RNG Parameters Definition
- 43.3.4.13.7. Options
- 43.3.4.13.8. Code Example
- 43.3.4.13.9. Constraints
- 43.3.4.13.10. Status Returned Values
- 43.3.5. Modular Arithmetic Services
- 43.3.5.1. Modular Reduction
- 43.3.5.1.1. Purpose
- 43.3.5.1.2. How to Use the Service
- 43.3.5.1.3. Description
- 43.3.5.1.4. Modular Reduction Setup
- 43.3.5.1.5. Fast Reductions and Normalization
- 43.3.5.1.6. Big Modular Reduction Using Euclide's Division
- 43.3.5.1.7. Modular Reductions Service Parameters Definition
- 43.3.5.1.8. Fast Modular Reductions Service Parameters Definition
- 43.3.5.1.9. Big Modular Reduction Parameters Definition
- 43.3.5.1.10. Options
- 43.3.5.1.11. Code Example
- 43.3.5.1.12. Constraints
- 43.3.5.1.13. Status Returned Values
- 43.3.5.2. Modular Exponentiation (Without CRT)
- 43.3.5.3. Probable Prime Generation (Using Rabin-Miller)
- 43.3.5.4. Modular Exponentiation (With CRT)
- 43.3.5.4.1. Purpose
- 43.3.5.4.2. How to Use the Service
- 43.3.5.4.3. Description
- 43.3.5.4.4. Parameters Definition
- 43.3.5.4.5. Options
- 43.3.5.4.6. Code Example
- 43.3.5.4.7. Constraints
- 43.3.5.4.8. CRT Service Parameter Placement
- 43.3.5.4.9. CRT Service Modular Exponentiation Maximum Size
- 43.3.5.4.10. Status Returned Values
- 43.3.5.1. Modular Reduction
- 43.3.6. Elliptic Curves Over GF(p) Services
- 43.3.6.1. Coordinate Systems
- 43.3.6.2. Point Addition
- 43.3.6.3. Point Addition and Subtraction
- 43.3.6.4. Fast Point Doubling
- 43.3.6.5. Fast Multiplying by a Scalar Number of a Point
- 43.3.6.6. Quick Dual Multiplying by Two Scalar Numbers and Two Points
- 43.3.6.7. Projective to Affine Coordinates Conversion
- 43.3.6.8. Affine to Projective Coordinates Conversion
- 43.3.6.9. Randomize a Coordinate
- 43.3.6.10. Point is on Elliptic Curve
- 43.3.6.11. Generating an ECDSA Signature (Compliant with FIPS 186-2)
- 43.3.6.12. Verifying an ECDSA Signature (Compliant with FIPS186-2)
- 43.3.6.13. Quick Verifying an ECDSA Signature (Compliant with FIPS 186-2)
- 43.3.7. Elliptic Curves Over GF(2n) Services
- 43.3.7.1. Parameters Format
- 43.3.7.2. Point Addition
- 43.3.7.3. Point Doubling
- 43.3.7.4. Scalar Point Multiply
- 43.3.7.5. Projective to Affine Coordinates Conversion
- 43.3.7.6. Affine to Projective Coordinates Conversion
- 43.3.7.7. Randomize Coordinate
- 43.3.7.8. Point is on Elliptic Curve
- 43.3.7.9. Generating an ECDSA Signature (Compliant with FIPS 186-2)
- 43.3.7.10. Verifying an ECDSA Signature (Compliant with FIPS 186-2)
- 43.3.8. PUKCL Requirements and Performance
- 44. TRNG – True Random Number Generator
- 45. ADC – Analog-to-Digital Converter
- 45.1. Overview
- 45.2. Features
- 45.3. Block Diagram
- 45.4. Signal Description
- 45.5. Product Dependencies
- 45.6. Functional Description
- 45.6.1. Principle of Operation
- 45.6.2. Basic Operation
- 45.6.2.1. Initialization
- 45.6.2.2. Enabling, Disabling, and Resetting
- 45.6.2.3. Operation
- 45.6.2.4. Prescaler Selection
- 45.6.2.5. Reference Configuration
- 45.6.2.6. ADC Resolution
- 45.6.2.7. Differential and Single-Ended Conversions
- 45.6.2.8. Conversion Timing and Sampling Rate
- 45.6.2.9. Accumulation
- 45.6.2.10. Averaging
- 45.6.2.11. Oversampling and Decimation
- 45.6.2.12. Window Monitor
- 45.6.2.13. Offset and Gain Correction
- 45.6.3. Additional Features
- 45.6.4. DMA Operation
- 45.6.5. Interrupts
- 45.6.6. Events
- 45.6.7. Sleep Mode Operation
- 45.6.8. Synchronization
- 45.7. Register Summary
- 45.8. Register Description
- 45.8.1. Control A
- 45.8.2. Event Control
- 45.8.3. Debug Control
- 45.8.4. Input Control
- 45.8.5. Control B
- 45.8.6. Reference Control
- 45.8.7. Average Control
- 45.8.8. Sampling Time Control
- 45.8.9. Window Monitor Lower Threshold
- 45.8.10. Window Monitor Upper Threshold
- 45.8.11. Gain Correction
- 45.8.12. Offset Correction
- 45.8.13. Software Trigger
- 45.8.14. Interrupt Enable Clear
- 45.8.15. Interrupt Enable Set
- 45.8.16. Interrupt Flag Status and Clear
- 45.8.17. STATUS
- 45.8.18. Synchronization Busy
- 45.8.19. DSEQDATA
- 45.8.20. DSEQCTRL
- 45.8.21. DSEQSTAT
- 45.8.22. Result
- 45.8.23. RESS
- 45.8.24. Calibration
- 46. AC – Analog Comparators
- 46.1. Overview
- 46.2. Features
- 46.3. Block Diagram
- 46.4. Signal Description
- 46.5. Product Dependencies
- 46.6. Functional Description
- 46.6.1. Principle of Operation
- 46.6.2. Basic Operation
- 46.6.3. Selecting Comparator Inputs
- 46.6.4. Window Operation
- 46.6.5. VDD Scaler
- 46.6.6. Input Hysteresis
- 46.6.7. Filtering
- 46.6.8. Comparator Output
- 46.6.9. Offset Compensation
- 46.6.10. DMA Operation
- 46.6.11. Interrupts
- 46.6.12. Events
- 46.6.13. Sleep Mode Operation
- 46.6.14. Synchronization
- 46.7. Register Summary
- 46.8. Register Description
- 46.8.1. Control A
- 46.8.2. Control B
- 46.8.3. Event Control
- 46.8.4. Interrupt Enable Clear
- 46.8.5. Interrupt Enable Set
- 46.8.6. Interrupt Flag Status and Clear
- 46.8.7. Status A
- 46.8.8. Status B
- 46.8.9. Debug Control
- 46.8.10. Window Control
- 46.8.11. Scaler n
- 46.8.12. Comparator Control n
- 46.8.13. Synchronization Busy
- 46.8.14. Calibration Register
- 47. DAC – Digital-to-Analog Converter
- 47.1. Overview
- 47.2. Features
- 47.3. Block Diagram
- 47.4. Signal Description
- 47.5. Product Dependencies
- 47.6. Functional Description
- 47.7. Register Summary
- 47.8. Register Description
- 47.8.1. Control A
- 47.8.2. Control B
- 47.8.3. Event Control
- 47.8.4. Interrupt Enable Clear
- 47.8.5. Interrupt Enable Set
- 47.8.6. Interrupt Flag Status and Clear
- 47.8.7. Status
- 47.8.8. Synchronization Busy
- 47.8.9. DAC0 Control
- 47.8.10. DAC1 Control
- 47.8.11. Data DAC0
- 47.8.12. Data DAC1
- 47.8.13. Data Buffer DAC0
- 47.8.14. Data Buffer DAC1
- 47.8.15. Debug Control
- 47.8.16. Result 0
- 47.8.17. Result 1
- 48. TC – Timer/Counter
- 48.1. Overview
- 48.2. Features
- 48.3. Block Diagram
- 48.4. Signal Description
- 48.5. Product Dependencies
- 48.6. Functional Description
- 48.6.1. Principle of Operation
- 48.6.2. Basic Operation
- 48.6.3. Additional Features
- 48.6.4. DMA Operation
- 48.6.5. Interrupts
- 48.6.6. Events
- 48.6.7. Sleep Mode Operation
- 48.6.8. Synchronization
- 48.7. Register Description
- 48.7.1. Register Summary - 8-bit Mode
- 48.7.1.1. Control A
- 48.7.1.2. Control B Clear
- 48.7.1.3. Control B Set
- 48.7.1.4. Event Control
- 48.7.1.5. Interrupt Enable Clear
- 48.7.1.6. Interrupt Enable Set
- 48.7.1.7. Interrupt Flag Status and Clear
- 48.7.1.8. Status
- 48.7.1.9. Waveform Generation Control
- 48.7.1.10. Driver Control
- 48.7.1.11. Debug Control
- 48.7.1.12. Synchronization Busy
- 48.7.1.13. Counter Value, 8-bit Mode
- 48.7.1.14. Period Value, 8-bit Mode
- 48.7.1.15. Channel x Compare/Capture Value, 8-bit Mode
- 48.7.1.16. Period Buffer Value, 8-bit Mode
- 48.7.1.17. Channel x Compare Buffer Value, 8-bit Mode
- 48.7.2. Register Summary - 16-bit Mode
- 48.7.2.1. Control A
- 48.7.2.2. Control B Clear
- 48.7.2.3. Control B Set
- 48.7.2.4. Event Control
- 48.7.2.5. Interrupt Enable Clear
- 48.7.2.6. Interrupt Enable Set
- 48.7.2.7. Interrupt Flag Status and Clear
- 48.7.2.8. Status
- 48.7.2.9. Waveform Generation Control
- 48.7.2.10. Driver Control
- 48.7.2.11. Debug Control
- 48.7.2.12. Synchronization Busy
- 48.7.2.13. Counter Value, 16-bit Mode
- 48.7.2.14. Channel x Compare/Capture Value, 16-bit Mode
- 48.7.2.15. Channel x Compare Buffer Value, 16-bit Mode
- 48.7.3. Register Summary - 32-bit Mode
- 48.7.3.1. Control A
- 48.7.3.2. Control B Clear
- 48.7.3.3. Control B Set
- 48.7.3.4. Event Control
- 48.7.3.5. Interrupt Enable Clear
- 48.7.3.6. Interrupt Enable Set
- 48.7.3.7. Interrupt Flag Status and Clear
- 48.7.3.8. Status
- 48.7.3.9. Waveform Generation Control
- 48.7.3.10. Driver Control
- 48.7.3.11. Debug Control
- 48.7.3.12. Synchronization Busy
- 48.7.3.13. Counter Value, 32-bit Mode
- 48.7.3.14. Channel x Compare/Capture Value, 32-bit Mode
- 48.7.3.15. Channel x Compare Buffer Value, 32-bit Mode
- 48.7.1. Register Summary - 8-bit Mode
- 49. TCC – Timer/Counter for Control Applications
- 49.1. Overview
- 49.2. Features
- 49.3. Block Diagram
- 49.4. Signal Description
- 49.5. Product Dependencies
- 49.6. Functional Description
- 49.6.1. Principle of Operation
- 49.6.2. Basic Operation
- 49.6.2.1. Initialization
- 49.6.2.2. Enabling, Disabling, and Resetting
- 49.6.2.3. Prescaler Selection
- 49.6.2.4. Counter Operation
- 49.6.2.5. Compare Operations
- 49.6.2.5.1. Waveform Output Generation Operations
- 49.6.2.5.2. Normal Frequency (NFRQ)
- 49.6.2.5.3. Match Frequency (MFRQ)
- 49.6.2.5.4. Normal Pulse-Width Modulation (NPWM)
- 49.6.2.5.5. Single-Slope PWM Operation
- 49.6.2.5.6. Dual-Slope PWM Generation
- 49.6.2.5.7. Dual-Slope Critical PWM Generation
- 49.6.2.5.8. Output Polarity
- 49.6.2.6. Double Buffering
- 49.6.2.7. Capture Operations
- 49.6.3. Additional Features
- 49.6.4. Master/Slave Operation
- 49.6.5. DMA, Interrupts, and Events
- 49.6.6. Sleep Mode Operation
- 49.6.7. Synchronization
- 49.7. Register Summary
- 49.8. Register Description
- 49.8.1. Control A
- 49.8.2. Control B Clear
- 49.8.3. Control B Set
- 49.8.4. Synchronization Busy
- 49.8.5. Fault Control A and B
- 49.8.6. Waveform Extension Control
- 49.8.7. Driver Control
- 49.8.8. Debug control
- 49.8.9. Event Control
- 49.8.10. Interrupt Enable Clear
- 49.8.11. Interrupt Enable Set
- 49.8.12. Interrupt Flag Status and Clear
- 49.8.13. Status
- 49.8.14. Counter Value
- 49.8.15. Pattern
- 49.8.16. Waveform
- 49.8.17. Period Value
- 49.8.18. Compare/Capture Channel x
- 49.8.19. Pattern Buffer
- 49.8.20. Period Buffer Value
- 49.8.21. Channel x Compare/Capture Buffer Value
- 50. PTC - Peripheral Touch Controller
- 51. I2S - Inter-IC Sound Controller
- 51.1. Overview
- 51.2. Features
- 51.3. Block Diagram
- 51.4. Signal Description
- 51.5. Product Dependencies
- 51.6. Functional Description
- 51.6.1. Principle of Operation
- 51.6.2. Basic Operation
- 51.6.3. Master, Controller, and Slave Modes
- 51.6.4. I2S Format - Reception and Transmission Sequence with Word Select
- 51.6.5. TDM Format - Reception and Transmission Sequence
- 51.6.6. PDM Reception
- 51.6.7. Data Formatting Unit
- 51.6.8. DMA, Interrupts and Events
- 51.6.9. Sleep Mode Operation
- 51.6.10. Synchronization
- 51.6.11. Loop-Back Mode
- 51.7. I2S Application Examples
- 51.8. Register Summary
- 51.9. Register Description
- 52. PCC - Parallel Capture Controller
- 53. PDEC – Position Decoder
- 53.1. Overview
- 53.2. Features
- 53.3. Block Diagram
- 53.4. Signal Description
- 53.5. Product Dependencies
- 53.6. Functional Description
- 53.6.1. Principle of Operation
- 53.6.2. Basic Operation
- 53.6.3. Additional Features
- 53.6.4. Interrupts
- 53.6.5. Events
- 53.6.6. Sleep Mode Operation
- 53.6.7. Synchronization
- 53.7. Register Summary
- 53.8. Register Description
- 53.8.1. Control A
- 53.8.2. Control B Clear
- 53.8.3. Control B Set
- 53.8.4. Event Control
- 53.8.5. Interrupt Enable Clear
- 53.8.6. Interrupt Enable Set
- 53.8.7. Interrupt Flag Status and Clear
- 53.8.8. Status
- 53.8.9. Debug Control
- 53.8.10. Synchronization Status
- 53.8.11. Prescaler Value
- 53.8.12. Filter Value
- 53.8.13. Prescaler Buffer Value
- 53.8.14. Filter Buffer Value
- 53.8.15. Counter Value
- 53.8.16. Channel x Compare Value
- 53.8.17. Channel x Compare Buffer Value
- 54. Electrical Characteristics at 85°C
- 54.1. Disclaimer
- 54.2. Absolute Maximum Ratings
- 54.3. General Operating Ratings
- 54.4. Injection Current
- 54.5. Supply Characteristics
- 54.6. Maximum Clock Frequencies
- 54.7. Power Consumption
- 54.8. Wake-Up Time
- 54.9. I/O Pin Characteristics
- 54.10. Analog Characteristics
- 54.10.1. Voltage Regulator Characteristics
- 54.10.2. Power-On Reset (POR) Characteristics
- 54.10.3. Brown-Out Detectors (BOD) Characteristics
- 54.10.4. Analog-to-Digital Converter (ADC) Characteristics
- 54.10.5. Digital to Analog Converter (DAC) Characteristics
- 54.10.6. Analog Comparator (AC) Characteristics
- 54.10.7. Voltage References
- 54.11. PTC Characteristics
- 54.12. NVM Characteristics
- 54.13. Oscillators Characteristics
- 54.13.1. Crystal Oscillator (XOSC) Characteristics
- 54.13.2. External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
- 54.13.3. Internal Ultra Low Power 32 kHz RC Oscillator (OSCULP32K) Characteristics
- 54.13.4. Digital Frequency Locked Loop (DFLL48M) Characteristics
- 54.13.5. Fractional Digital Phase Lock Loop (FDPLL) Characteristics
- 54.14. Timing Characteristics
- 54.15. USB Characteristics
- 55. Electrical Characteristics at 105°C
- 55.1. General Operating Ratings (105°C)
- 55.2. Supply Characteristics (105°C)
- 55.3. Power Consumption (105°C)
- 55.4. Analog Characteristics (105°C)
- 55.4.1. Power-On Reset (POR) Characteristics (105°C)
- 55.4.2. Brown-Out Detectors (BOD) Characteristics (105°C)
- 55.4.3. Analog-to-Digital Converter (ADC) Characteristics (105°C)
- 55.4.4. Digital to Analog Converter (DAC) Characteristics (105°C)
- 55.4.5. Analog Comparator (AC) Characteristics (105°C)
- 55.4.6. PTC Characteristics
- 55.5. NVM Characteristics
- 55.6. Oscillators Characteristics (105°C)
- 55.6.1. Crystal Oscillator (XOSC) Characteristics (105°C)
- 55.6.2. External 32 kHz Crystal Oscillator (XOSC32K) Characteristics (105°C)
- 55.6.3. Internal Ultra Low Power 32 kHz RC Oscillator (OSCULP32K) Characteristics (105°C)
- 55.6.4. Digital Frequency Locked Loop (DFLL48M) Characteristics (105°C)
- 55.6.5. Fractional Digital Phase Lock Loop (FDPLL) Characteristics (105°C)
- 56. Electrical Characteristics at 125°C
- 56.1. General Operating Ratings (125°C)
- 56.2. Injection Current (125°C)
- 56.3. Supply Characteristics (125°C)
- 56.4. Maximum Clock Frequencies (125°C)
- 56.5. Power Consumption (125°C)
- 56.6. Analog Characteristics (125°C)
- 56.6.1. Power-On Reset (POR) Characteristics (125°C)
- 56.6.2. Brown-Out Detectors (BOD) Characteristics (125°C)
- 56.6.3. Analog-to-Digital Converter (ADC) Characteristics (125°C)
- 56.6.4. Digital-to-Analog Converter (DAC) Characteristics (125°C)
- 56.6.5. Analog Comparator (AC) Characteristics (125°C)
- 56.6.6. PTC Characteristics
- 56.7. NVM Characteristics (125°C)
- 56.8. Oscillators Characteristics (125°C)
- 56.8.1. Crystal Oscillator (XOSC) Characteristics (125°C)
- 56.8.2. External 32 kHz Crystal Oscillator (XOSC32K) Characteristics (125°C)
- 56.8.3. Internal Ultra Low Power 32 kHz RC Oscillator (OSCULP32K) Characteristics (125°C)
- 56.8.4. Digital Frequency Locked Loop (DFLL48M) Characteristics (125°C)
- 56.8.5. Fractional Digital Phase Lock Loop (FDPLL) Characteristics (125°C)
- 56.9. Timing Characteristics (125°C)
- 57. AEC Q-100 Grade 1, 125°C Electrical Characteristics
- 58. Packaging Information
- 59. Schematic Checklist
- 60. Conventions
- 61. Acronyms and Abbreviations
- 62. Revision History
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This bit is set at the falling edge of the DAT Line Active (DLACT) status. This interrupt is generated in two
cases. The first is when the last data is written to the card as specified by the data length and the Busy
signal is released. The second is when data transfers are stopped at the block gap by setting Stop At
Block Gap Request (STPBGR) in BGCR and data transfers are completed. (After valid data is written to
the card and the Busy signal is released). Refer to section “Write Transaction Wait / Continue Timing” in
the “SD Host Controller Simplified Specification V3.00” for more details on the sequence of events.
In the case of command with Busy:
This bit is set when Busy is de-asserted. Refer to DAT Line Active (DLACT) and Command Inhibit (DAT)
(CMDINHD) in PSR.
This bit can only be set to 1 if NISTER.TRFC is set to 1. An interrupt can only be generated if
NISIER.TRFC is set to 1.
Writing this bit to 1 clears this bit.
The table below shows that Transfer Complete (TRFC) has a higher priority than Data Timeout Error
(DATTEO). If both bits are set to 1, execution of a command can be considered to be completed.
TRFC DATTEO Meaning of the status
0 0 Interrupted by another factor
0 1 Timeout occurred during transfer
1 Don’t Care Command execution complete
Value Description
0
Command execution is not complete.
1
Command execution is complete.
Bit 0 – CMDC Command Complete
This bit is set when getting the end bit of the command response. Auto CMD12 and Auto CMD23 consist
of two responses. Command Complete is not generated by the response of CMD12 or CMD23, but it is
generated by the response of a read/write command. Refer to Command Inhibit (CMD) in PSR for details
on how to control this bit.
This bit can only be set to 1 if NISTER.CMDC is set to 1. An interrupt can only be generated if
NISIER.CMDC is set to 1.
Writing this bit to 1 clears this bit.
The table below shows that Command Timeout Error (CMDTEO) has a higher priority than Command
Complete (CMDC). If both bits are set to 1, it can be considered that the response was not received
correctly.
CMDC CMDTEO Meaning of the status
0 0 Interrupted by another factor
Don’t care 1 Response not received within 64 SDCLK cycles
1 0 Response received
Value Description
0
No command complete
1
Command complete
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1350