Datasheet

40.8.17 Normal Interrupt Status Register
Name: NISTR
Offset: 0x30
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
ERRINT BOOTAR CINT
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
CREM CINS BRDRDY BWRRDY DMAINT BLKGE TRFC CMDC
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 – ERRINT Error Interrupt
If any of the bits in EISTR are set, then this bit is set. Therefore, the user can efficiently test for an error
by checking this bit first. This bit is read-only.
Value Description
0
No error
1
Error
Bit 14 – BOOTAR Boot Acknowledge Received
Note: This register entry is specific to the e.MMC operation mode.
This bit is set to 1 when the peripheral received a Boot Acknowledge pattern from the e.MMC.
This bit can only be set to 1 if NISTER.BOOTAR is set to 1. An interrupt can only be generated if
NISIER.BOOTAR is set to 1.
Writing this bit to 1 clears this bit.
Value Description
0
Boot Acknowledge pattern not received.
1
Boot Acknowledge pattern received.
Bit 8 – CINT Card Interrupt
Note:
This register entry is specific to the SD/SDIO operation mode.
Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit
mode, the peripheral detects the Card Interrupt without SDCLK to support wake-up. In 4-bit mode, the
Card Interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the
interrupt signal from the SD card and the interrupt to the system.
When this bit has been set to 1 and the user needs to start this interrupt service, Card Interrupt Status
Enable (CINT) in NISTER may be set to 0 in order to clear the card interrupt statuses latched in the
peripheral and to stop driving the interrupt signal to the system. After completion of the card interrupt
service (it should reset interrupt factors in the SD card and the interrupt signal may not be asserted), set
NISTER.CINT to 1 and start sampling the interrupt signal again.
Interrupt detected by DAT[1] is supported when there is one card per slot. In case of a shared bus,
interrupt pins are used to detect interrupts. If 0 is set to Interrupt Pin Select (INTPSEL) in SBCR, this
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
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Datasheet
DS60001507E-page 1347