Datasheet

Value Description
0
Work
1
Reset
Bit 0 – SWRSTALL Software reset for All
This reset affects the entire peripheral except the card detection circuit. During initialization, the peripheral
must be reset by setting this bit to 1. This bit is automatically cleared to 0 when CA0R and CA1R are valid
and the user can read them. If this bit is set to 1, the user should issue a reset command and reinitialize
the card.
List of registers cleared to 0:
• SDMA System Address / Argument 2 Register 40.8.1 SSAR
• Block Size Register 40.8.2 BSR
• Block Count Register 40.8.3 BCR
• Argument 1 Register 40.8.4 ARG1R
• Transfer Mode Register 40.8.5 TMR
• Command Register 40.8.6 CR
• Response Register n 40.8.7 RR
• Buffer Data Port Register 40.8.8 BDPR
• Present State Register 40.8.9 PSR (except CMDLL, DATLL, WRPPL, CARDDDPL, CARDSS,
CARDINS)
• Host Control 1 Register 40.8.10 HC1R
• Power Control Register 40.8.11 PCR
• Block Gap Control Register 40.8.12 BGCR
• Wakeup Control Register 40.8.13 WCR
• Clock Control Register 40.8.14 CCR
• Timeout Control Register 40.8.15 TCR
• Normal Interrupt Status Register 40.8.17 NISTR
• Error Interrupt Status Register 40.8.18 EISTR
• Normal Interrupt Status Enable Register 40.8.19 NISTER
• Error Interrupt Status Enable Register 40.8.20 EISTER
• Normal Interrupt Signal Enable Register 40.8.21 NISIER
• Error Interrupt Signal Enable Register 40.8.22 EISIER
• Auto CMD Error Status Register 40.8.23 ACESR
• Host Control 2 Register 40.8.25 HC2R - DEFAULT
• ADMA Error Status Register 40.8.31 AESR
• ADMA System Address Registers 40.8.32 ASAR
• Slot Interrupt Status Register 40.8.34 SISR
• e.MMC Control 1 Register 40.8.37 MC1R
• e.MMC Control 2 Register 40.8.38 MC2R
• AHB Control Register 40.8.39 ACR
• Clock Control 2 Register 40.8.40 CC2R
• Capabilities Control Register 40.8.41 CACR (except KEY)
Value Description
0
Work
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1345