Datasheet

40.8.16 Software Reset Register
Name: SRR
Offset: 0x2F
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SWRSTDAT SWRSTCMD SWRSTALL
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – SWRSTDAT Software reset for DAT line
Only part of a data circuit is reset. The DMA circuit is also reset.
The following registers and bits are cleared by this bit:
• Buffer Data Port Register 40.8.8 BDPR: BUFDATA is cleared and initialized.
• Present State Register 40.8.9 PSR:
– Buffer Read Enable (BUFRDEN)
– Buffer Write Enable (BUFWREN)
– Read Transfer Active (RTACT)
– Write Transfer Active (WTACT)
– DAT Line Active (DATLL)
– Command Inhibit - DAT (CMDINHD)
• Block Gap Control Register 40.8.12 BGCR:
– Continue Request (CONTR)
– Stop At Block Gap Request (STPBGR)
• Normal Interrupt Status Register 40.8.17 NISTR:
– Buffer Read Ready (BRDRDY)
– Buffer Write Ready (BWRRDY)
– DMA Interrupt (DMAINT)
– Block Gap Event (BLKGE)
– Transfer Complete (TRFC)
Value Description
0
Work
1
Reset
Bit 1 – SWRSTCMD Software reset for CMD line
Only part of a command circuit is reset.
The following registers and bits are cleared by this bit:
• Present State Register 40.8.9 PSR:
– Command Inhibit (CMD) (CMDINHC)
• Normal Interrupt Status Register 40.8.17 NISTR:
– Command Complete (CMDC)
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1344