Datasheet

Bit 2 – SDCLKEN SD Clock Enable
The peripheral stops the SD Clock when writing this bit to 0. SDCLK Frequency Select (SDCLKFSEL)
can be changed when this bit is 0. Then, the peripheral maintains the same clock frequency until SDCLK
is stopped (Stop at SDCLK=0). If Card Inserted (CARDINS) in PSR is cleared, this bit is also cleared.
Value Description
0
SD Clock disabled
1
SD Clock enabled
Bit 1 – INTCLKS Internal Clock Stable
This bit is set to 1 when the SD clock is stable after setting CCR.INTCLKEN (Internal Clock Enable) to 1.
The user must wait to set SD Clock Enable (SDCLKEN) until this bit is set to 1.
Value Description
0
Internal clock not ready
1
Internal clock ready
Bit 0 – INTCLKEN Internal Clock Enable
This bit is set to 0 when the peripheral is not used or is awaiting a wakeup interrupt. In this case, its
internal clock is stopped to reach a very low power state. Registers are still able to be read and written.
The clock starts to oscillate when this bit is set to 1. Once the clock oscillation is stable, the peripheral
sets Internal Clock Stable (INTCLKS) in this register to 1.
This bit does not affect card detection.
Value Description
0
The internal clock stops.
1
The internal clock oscillates.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1342