Datasheet

40.8.14 Clock Control Register
Name: CCR
Offset: 0x2C
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
SDCLKFSEL[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
USDCLKFSEL[1:0] CLKGSEL SDCLKEN INTCLKS INTCLKEN
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 15:8 – SDCLKFSEL[7:0] SDCLK Frequency Select
This register is used to select the frequency of the SDCLK pin. There are two SDCLK Frequency modes
according to Clock Generator Select (CLKGSEL).
The length of the clock divider (DIV) is extended to 10 bits (DIV[9:8] = USDCLKFSEL, DIV[7:0] =
SDCLKFSEL)
– 10-bit Divided Clock Mode (CLKGSEL = 0):

SDCLK
= 
BASECLK
/ 2 × DIV
. If DIV = 0 then

SDCLK
= 
BASECLK
– Programmable Clock Mode (CLKGSEL = 1):

SDCLK
= 
MULTCLK
/ DIV+1
This field depends on the setting of Preset Value Enable (PVALEN) in HC2R.
If HC2R.PVALEN = 0, this field is set by the user.
If HC2R.PVALEN = 1, this field is automatically set to a value specified in one of the PVR.
Bits 7:6 – USDCLKFSEL[1:0] Upper Bits of SDCLK Frequency Select
These bits expand the SDCLK Frequency Select (SDCLKFSEL) to 10 bits. These two bits are assigned
to bit 09-08 of the clock divider as described in SDCLKFSEL.
Bit 5 – CLKGSEL Clock Generator Select
This bit is used to select the clock generator mode in the SDCLK Frequency Select field. If the
Programmable mode is not supported (CA1R.CLKMULT (Clock Multiplier) set to 0), then this bit cannot
be written and is always read at 0.
This bit depends on the setting of Preset Value Enable (PVALEN) in HC2R.
If HC2R.PVALEN = 0, this bit is set by the user.
If HC2R.PVALEN = 1, this bit is automatically set to a value specified in one of the PVRx.
Value Description
0
Divided Clock mode (BASECLK is used to generate SDCLK).
1
Programmable Clock mode (MULTCLK is used to generate SDCLK).
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1341