Datasheet

Value Description
0
No affect
1
Restart
Bit 0 – STPBGR Stop At Block Gap Request
This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA,
and ADMA transfers. The user must leave this bit set to 1 until Transfer Complete (TRFC) in NISTR.
Clearing both Stop At Block Gap Request and Continue Request does not cause the transaction to
restart. This bit can be set whether the card supports the Read Wait signal or not.
During read transfers, the peripheral stops the transaction by using the Read Wait signal (DAT[2]) if
supported, or by stopping the SD clock otherwise.
In case of write transfers in which the user writes data to BDPR, this bit must be set to 1 after all the block
of data is written. If this bit is set to 1, the user does not write data to BDPR.
This bit affects Read Transfer Active (RTACT), Write Transfer Active (WTACT), DAT Line Active (DLACT)
and Command Inhibit (DAT) (CMDINHD) in PSR.
Refer to the “Abort Transaction” and “Suspend/Resume” sections in the “SD Host Controller Simplified
Specification V3.00” for more details.
Value Description
0
Transfer
1
Stop
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1339