Datasheet

40.8.12 Block Gap Control Register
Name: BGCR
Offset: 0x2A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
INTBG RWCTRL CONTR STPBGR
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 3 – INTBG Interrupt at Block Gap
Note:
This register entry is specific to the SD/SDIO operation mode.
This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle.
Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SDIO card
cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. When the software
detects an SDIO card insertion, it sets this bit according to the CCCR of the SDIO card.
Value Name Description
0
DISABLED Interrupt detection disabled
1
ENABLED Interrupt detection enabled
Bit 2 – RWCTRL Read Wait Control
Note:
This register entry is specific to the SD/SDIO operation mode.
The Read Wait control is optional for SDIO cards. If the card supports Read Wait, set this bit to enable
use of the Read Wait protocol to stop read data using the DAT[2] line. Otherwise, the peripheral stops the
SDCLK to hold read data, which restricts command generation. When the software detects an SD card
insertion, this bit must be set according to the CCCR of the SDIO card. If the card does not support Read
Wait, this bit shall never be set to 1, otherwise an DAT line conflict may occur. If this bit is set to 0,
Suspend/Resume cannot be supported.
Value Description
0
Disables Read Wait control.
1
Enables Read Wait control.
Bit 1 – CONTR Continue Request
This bit is used to restart a transaction which was stopped using a Stop At Block Gap Request
(STPBGR). To cancel stop at the block gap, set STPBGR to 0 and set this bit to 1 to restart the transfer.
The peripheral automatically clears this bit in either of the following cases:
• In the case of a read transaction, the DAT Line Active (DLACT) changes from 0 to 1 as a read
transaction restarts.
• In the case of a write transaction, the Write Transfer Active (WTACT) changes from 0 to 1 as the
write transaction restarts.
Therefore, it is not necessary to set this bit to 0. If STPBGR is set to 1, any write to this bit is ignored.
Refer to the “Abort Transaction” and “Suspend/Resume” sections in the “SD Host Controller Simplified
Specification V3.00” for more details.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1338