Datasheet

The peripheral stops a read operation at the start of the interrupt cycle by driving the Read Wait (DAT[2]
line) or by stopping the SD Clock. If the Read Wait signal is already driven (due to the fact that the data
buffer cannot receive data), the peripheral can continue to stop the read operation by driving the Read
Wait signal. It is necessary to support the Read Wait in order to use the Suspend/Resume operation.
In the case of write transactions:
This status indicates that a write transfer is executing on the bus. A change from 1 to 0 rises the Transfer
Complete (TRFC) status flag in NISTR if NISTER.TRFC is set to 1. An interrupt is generated if
NISIER.TRFC is set to 1. Refer to section “Write Transaction Wait / Continue Timing” in the “SD Host
Controller Simplified Specification V3.00” for details on timing.
This bit is set in either of the following cases:
• After the end bit of the write command.
• When writing 1 to BGCR.CONTR (Continue Request) to continue a write transfer.
This bit is cleared in either of the following cases:
• When the card releases Write Busy of the last data block. If the card does not drive a Busy signal for
8 SDCLK, the peripheral considers the card drive “Not Busy”. In the case of ADMA2, the last block is
designated by the last transfer of the Descriptor Table.
• When the card releases Write Busy prior to wait for write transfer as a result of a Stop At Block Gap
Request (STPBGR).
Command with Busy:
This status indicates whether a command that indicates Busy (ex. erase command for memory) is
executing on the bus. This bit is set to 1 after the end bit of the command with Busy and cleared when
Busy is de-asserted. A change from 1 to 0 rises the Transfer Complete (TRFC) status flag in NISTR if
NISTER.TRFC is set to 1. An interrupt is generated if NISIER.TRFC is set to 1. Refer to Figures 2.11 to
2.13 in the “SD Host Controller Simplified Specification V3.00”.
Value Description
0
DAT Line Inactive
1
DAT Line Active
Bit 1 – CMDINHD Command Inhibit (DAT)
This status bit is 1 if either the DAT Line Active (DLACT) or the Read Transfer Active (RTACT) is set to 1.
If this bit is 0, it indicates that the peripheral can issue the next command. Commands with a Busy signal
belong to Command Inhibit (DAT) (ex. R1b, R5b type). A change from 1 to 0 rises the Transfer Complete
(TRFC) status flag in NISTR if NISTER.TRFC is set to 1. An interrupt is generated if NISIER.TRFC is set
to 1.
Note: The software can save registers in the 000-00Dh range for a suspend transaction after this bit has
changed from 1 to 0.
Value Description
0
Can issue a command which uses the DAT line(s).
1
Cannot issue a command which uses the DAT line(s).
Bit 0 – CMDINHC Command Inhibit (CMD)
If this bit is 0, it indicates the CMD line is not in use and the peripheral can issue a command using the
CMD line. This bit is set to 1 immediately after CR is written. This bit is cleared when the command
response is received. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not
cleared by the CMD12 or CMD23 response, but by the Read/Write command response.
Status issuing Auto CMD12 is not read from this bit. So, if a command is issued during Auto CMD12
operation, the peripheral manages to issue both commands: CMD12 and a command set by CR.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1333