Datasheet

Bit 8 – WTACT Write Transfer Active
This bit indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the
peripheral. Refer to section “Write Transaction Wait / Continue Timing” in the “SD Host Controller
Simplified Specification V3.00” for more details on the sequence of events.
This bit is set to 1 in either of the following conditions:
• After the end bit of the write command.
• When a write operation is restarted by writing a 1 to BGCR.CONTR (Continue Request).
This bit is cleared to 0 in either of the following conditions:
• After getting the CRC status of the last data block as specified by the transfer count (single and
multiple). In case of ADMA2, transfer count is designated by the descriptor table.
• After getting the CRC status of any block where a data transmission is about to be stopped by a Stop
At Block Gap Request (STPBGR) of BGCR.
During a write transaction and as the result of the Stop At Block Gap Request (STPBGR) being set, a
change from 1 to 0 rises the Block Gap Event (BLKGE) status flag in NISTR if NISTER.BLKGE is set to 1.
An interrupt is generated if BLKGE is set to 1 in NISIER. This status is useful to determine whether non-
DAT line commands can be issued during Write Busy.
Bit 3 – RTREQ Retuning Request
The peripheral can instruct the software to execute a re-tuning sequence by setting this bit when the data
window is shifted by a temperature drift and a tuned sampling point does not have a good margin to
receive correct data.
This bit is cleared to 0 when a command is issued by setting Execute Tuning (EXTUN) in HC2R.
A change from 0 to 1 rises the Re-Tuning Event (RTEVT) status flag in NISTR if NISTER.RTEVT is set to
1. An interrupt is generated if NISIER.RTEVT is set to 1.
This bit is not set to 1 if Sampling Clock Select (SCLKSEL) in HC2R is set to 0 (using a fixed sampling
clock). Refer to Re-Tuning Modes (RTMODE) in CA1R.
Value Description
0
Fixed or well-tuned sampling clock
1
Sampling clock needs re-tuning
Bit 2 – DLACT DAT Line Active
This bit indicates whether one of the DAT lines on the bus is in use.
In the case of read transactions:
This status indicates whether a read transfer is executing on the bus. A change from 1 to 0 resulting from
setting the Stop At Block Gap Request (STPBGR) rises the Block Gap Event (BLKGE) status flag in
NISTR if NISTER.BLKGE is set to 1. An interrupt is generated if NISIER.BLKGE is set to 1. Refer to
section “Read Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification
V3.00” for details on timing.
This bit is set in either of the following cases:
• After the end bit of the read command.
• When writing 1 to BGCR.CONTR (Continue Request) to restart a read transfer.
This bit is peripheral cleared in either of the following cases:
• When the end bit of the last data block is sent from the bus to the peripheral. In case of ADMA2, the
last block is designated by the last transfer of the Descriptor Table.
• When a read transfer is stopped at the block gap initiated by a Stop At Block Gap Request
(STPBGR).
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1332