Datasheet

Bit 17 – CARDSS Card State Stable
This bit is used for testing. If it is 0, the CARDDPL is not stable. If this bit is set to 1, it means that the
CARDDPL is stable. No Card state can be detected if this bit is set to 1 and CARDINS is set to 0.
The Software Reset For All (SWRSTALL) in SRR does not affect this bit.
Value Description
0
Reset or debouncing
1
No card or card inserted
Bit 16 – CARDINS Card Inserted
This bit indicates whether a card has been inserted. The peripheral debounces this signal so that the user
does not need to wait for it to stabilize.
A change from 0 to 1 rises the Card Insertion (CINS) status flag in NISTR if NISTER.CINS is set to 1. An
interrupt is generated if NISIER.CINS is set to 1.
A change from 1 to 0 rises the Card Removal (CREM) status flag in NISTR if NISTER.CREM is set to 1.
An interrupt is generated if NISIER.CREM is set to 1.
The Software Reset For All (SWRSTALL) in SRR does not affect this bit.
Bit 11 – BUFRDEN Buffer Read Enable
This bit is used for non-DMA read transfers. This flag indicates that valid data exists in the peripheral data
buffer. If this bit is 1, readable data exists in the buffer.
A change from 1 to 0 occurs when all the block data is read from the buffer.
A change from 0 to 1 occurs when block data is ready in the buffer. This rises the Buffer Read Ready
(BRDRDY) status flag in NISTR if NISTER.BRDRDY is set to 1. An interrupt is generated if
NISIER.BRDRDY is set to 1.
Bit 10 – BUFWREN Buffer Write Enable
This bit is used for non-DMA write transfers. This flag indicates if space is available for write data. If this
bit is 1, data can be written to the buffer.
A change from 1 to 0 occurs when all the block data are written to the buffer.
A change from 0 to 1 occurs when top of block data can be written to the buffer. This rises the Buffer
Write Ready (BRWRDY) status flag in NISTR if NISTER.BRWRDY is set to 1. An interrupt is generated if
NISIER.BRWRDY is set to 1.
Bit 9 – RTACT Read Transfer Active
This bit is used to detect completion of a read transfer. Refer to section “Read Transaction Wait /
Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for more details on the
sequence of events.
This bit is set to 1 in either of the following conditions:
• After the end bit of the read command.
• When a read operation is restarted by writing a 1 to BGCR.CONTR (Continue Request).
This bit is cleared to 0 in either of the following conditions:
• When the last data block as specified by Transfer Block Size (BLKSIZE) is transferred to the system.
• In case of ADMA2, end of read is designated by the descriptor table.
• When all valid data blocks in the peripheral have been transferred to the system and no current block
transfers are being sent as a result of the Stop At Block Gap Request (STPBGR) of BGCR being set
to 1.
A change from 1 to 0 rises the Transfer Complete (TRFC) status flag in NISTR if NISTER.TRFC is set to
1. An interrupt is generated if NISIER.TRFC is set to 1.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1331