Datasheet

40.8.9 Present State Register
Name: PSR
Offset: 0x24
Reset: 0x00F80000
Property: -
Bit 31 30 29 28 27 26 25 24
CMDLL
Access
R
Reset 0
Bit 23 22 21 20 19 18 17 16
DATLL[3:0] WRPPL CARDDPL CARDSS CARDINS
Access
R R R R R R R R
Reset 1 1 1 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8
BUFRDEN BUFWREN RTACT WTACT
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RTREQ DLACT CMDINHD CMDINHC
Access
R R R R
Reset 0 0 0 0
Bit 24 – CMDLL CMD Line Level
This status is used to check the CMD line level to recover from errors, and for debugging.
Bits 23:20 – DATLL[3:0] DAT[3:0] Line Level
This status is used to check the DAT line level to recover from errors, and for debugging. This is
especially useful in detecting the Busy signal level from DAT[0].
Bit 19 – WRPPL Write Protect Pin Level
The Write Protect Switch is supported for memory and combo cards. This bit reflects the WP pin.
Value Description
0
Write protected (WP = 0)
1
Write enabled (WP = 1)
Bit 18 – CARDDPL Card Detect Pin Level
This bit reflects the inverse value of the CD pin. Debouncing is not performed on this bit. This bit may be
valid when CARDSS is set to 1, but it is not guaranteed because of the propagation delay. Use of this bit
is limited to testing since it must be debounced by software.
Value Description
0
No card present (CD = 1)
1
Card present (CD = 0)
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1330