Datasheet

40.8.7 Response Register n
Name: RR
Offset: 0x10 + n*0x04 [n=0..3]
Reset: 0x000000000
Property: -
Bit 31 30 29 28 27 26 25 24
CMDRESP[31:24]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CMDRESP[23:16]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CMDRESP[15:8]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMDRESP[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – CMDRESP[31:0] Command Response
The table below describes the mapping of command responses from the SD/SDIO/e.MMC bus to these
registers for each responses type. In this table, R[] refers to a bit range of the response data as
transmitted on the SD/SDIO/e.MMC bus.
Type of response Meaning of response Response field Response register
R1, R1b (normal response) Card Status R[39:8] RR0[31:0]
R1b (Auto CMD12 response) Card Status for Auto CMD12 R[39:8] RR3[31:0]
R1 (Auto CMD23 response) Card Status for Auto CMD23 R[39:8] RR3[31:0]
R2 (CID, CSD register) CID or CSD register R[127:8] RR0[31:0]
RR1[31:0]
RR2[31:0]
RR3[23:0]
R3 (OCR register) OCR register for memory R[39:8] RR0[31:0]
R4 (OCR register) OCR register for I/O R[39:8] RR0[31:0]
R5, R5b SDIO response R[39:8] RR0[31:0]
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1327