Datasheet

40.8.1 SDMA System Address / Argument 2 Register
Name: SSAR
Offset: 0x00
Reset: 0x00000000
Property: -
This register contains the physical system memory address used for SDMA transfers or the second
argument for Auto CMD23.
Bit 31 30 29 28 27 26 25 24
ARG2[31:24]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
ARG2[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ARG2[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ARG2[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – ARG2[31:0] SDMA System Address/Argument 2
The function of this bit field is depending on the operation mode:
For a SDMA transfer, this field is the system memory address. When the peripheral stops an SDMA
transfer, this field points to the system address of the next contiguous data position. This field can be
accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations
during transfers may return an invalid value. An interrupt can be generated to instruct the software to
update this field. Writing the next system address of the next data position restarts the SDMA transfer.
When executing Auto CMD23, this field is used with Auto CMD23 to set a 32-bit block count value to the
CMD23 argument. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If
Auto CMD23 is used without ADMA, the available block count value is limited by BCR. In this case,
65535 blocks is the maximum value.
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1319