Datasheet

The two generic clocks are:
• The core clock GCLK_SDHCx is required to clock the SDHC core.
• The slow clock GCLK_SDHCx_SLOW is only required for certain functions. When this clock is
required, GCLK_SDHCx must be enabled.
These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the
SDHC. The generic clocks are asynchronous to the user interface clock (CLK_SDHCx_AHB). Due to this
asynchronicity, writing to certain registers will require synchronization between the clock domains.
Related Links
15. MCLK – Main Clock
40.5.4 DMA
Not applicable.
40.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first.
40.5.6 Events
Not applicable.
40.6 Functional Description
40.6.1 SD/SDIO Operating Mode
This peripheral is fully compliant with the "SD Host Controller Simplified Specification V3.00" for SD/SDIO
devices. Refer to this specification for configuration.
Refer to "Physical Layer Simplified Specification V3.01" and "SDIO Simplified Specification V3.00" for SD/
SDIO management.
Related Links
40.1.1 Reference Documents
40.6.2 e.MMC Operating Mode
This peripheral supports e.MMC devices management. As the “SD Host Controller Simplified
Specification V3.00” does not apply to e.MMC devices, some registers have been added to those
described in this specification in order to manage e.MMC devices. Most of the registers described in the
“SD Host Controller Simplified Specification V3.00” must be used for e.MMC management, but e.MMC-
specific features are managed using MC1R and MC2R.
Related Links
40.1.1 Reference Documents
SAM D5x/E5x Family Data Sheet
SD/MMC Host Controller ...
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1314