Datasheet

Figure 39-12. Message RAM Configuration
11-bit Filter
29-bit Filter
Rx FIFO 0
Rx FIFO 1
Rx Buffers
Tx Event FIFO
Tx Buffers
0-128 elements / 0-128 words
0-64 elements / 0-128 words
0-64 elements / 0-1152 words
0-64 elements / 0-1152 words
0-64 elements / 0-1152 words
0-32 elements / 0-64 words
0-32 elements / 0-576 words
SIDFC.FLSSA
XIDFC.FLESA
RXF0C.F0SA
RXF1C.F1SA
RXBC.RBSA
TXEFC.EFSA
TXBC.TBSA
32 bit
max 4352 words
Start Address
When the CAN addresses the Message RAM it addresses 32-bit words, not single bytes. The
configurable start addresses are 32-bit word addresses (i.e. only bits 15 to 2 are evaluated and the two
LSBs are ignored).
WARNING
The CAN does not check for erroneous configuration of the Message RAM. Especially the
configuration of the start addresses of the different sections and the number of elements of
each section has to be done carefully to avoid falsification or loss of data.
39.9.2 Rx Buffer and FIFO Element
Up to 64 Rx Buffers and two Rx FIFOs can be configured in the Message RAM. Each Rx FIFO section
can be configured to store up to 64 received messages. The structure of a Rx Buffer / FIFO element is
shown in the table below. The element size can be configured for storage of CAN FD messages with up
to 64 bytes data field via register RXESC.
Table 39-8. Rx Buffer and FIFO Element
31 3
0
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
E
S
I
X
T
D
R
T
R
ID[28:0]
R1
A
N
M
F
FIDX[6:0]
F
D
F
B
R
S
DLC[3:0] RXTS[15:0]
R2 DB3[7:0] DB2[7:0] DB1[7:0] DB0[7:0]
R3 DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0]
... ... ... ... ...
Rn DBm[7:0] DBm-1[7:0] DBm-2[7:0] DBm-3[7:0]
• R0 Bit 31 - ESI: Error State Indicator
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1302