Datasheet

39.8.47 Tx Event FIFO Acknowledge
Name: TXEFA
Offset: 0xF8
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
EFAI[4:0]
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 4:0 – EFAI[4:0] Event FIFO Acknowledge Index
After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the
index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index
TXEFS.EFGI to EFAI + 1 and update the FIFO 0 Fill Level TXEFS.EFFL.
39.9 Message RAM
For storage of Rx/Tx messages and for storage of the filter configuration a single- or dual-ported
Message RAM has to be connected to the CAN module.
39.9.1 Message RAM Configuration
The Message RAM has a width of 32 bits. In case parity checking or ECC is used a respective number of
bits has to be added to each word. The CAN module can be configured to allocate up to 4352 words in
the Message RAM. It is not necessary to configure each of the sections listed in the figure below, nor is
there any restriction with respect to the sequence of the sections.
When operated in CAN FD mode the required Message RAM size strongly depends on the element size
configured for Rx FIFO 0, Rx FIFO 1, Rx Buffers, and Tx Buffers via RXESC.F0DS, RXESC.F1DS,
RXESC.RBDS, and TXESC.TBDS.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1301