Datasheet

39.8.46 Tx Event FIFO Status
Name: TXEFS
Offset: 0xF4
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
TEFL EFF
Access
R R
Reset 0 0
Bit 23 22 21 20 19 18 17 16
EFPI[4:0]
Access
R R R R R
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
EFGI[4:0]
Access
R R R R R
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EFFL[4:0]
Access
R R R R R
Reset 0 0 0 0 0
Bit 25 – TEFL Tx Event FIFO Element Lost
This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.
Value Description
0
No Tx Event FIFO element lost.
1
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
Bit 24 – EFF Event FIFO Full
Value Description
0
Tx Event FIFO not full.
1
Tx Event FIFO full.
Bits 20:16 – EFPI[4:0] Event FIFO Put Index
Tx Event FIFO write index pointer, range 0 to 31.
Bits 12:8 – EFGI[4:0] Event FIFO Get Index
Tx Event FIFO read index pointer, range 0 to 31.
Bits 4:0 – EFFL[4:0] Event FIFO Fill Level
Number of elements stored in Tx Event FIFO, range 0 to 32.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1300