Datasheet

39.8.45 Tx Event FIFO Configuration
Name: TXEFC
Offset: 0xF0
Reset: 0x00000000
Property: Write-restricted
This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
Bit 31 30 29 28 27 26 25 24
EFWM[5:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
EFS[5:0]
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
EFSA[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EFSA[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 29:24 – EFWM[5:0] Event FIFO Watermark
Value Description
0
Watermark interrupt disabled.
1 - 32
Level for Tx Event FIFO watermark interrupt (IR.TEFW).
>32
Watermark interrupt disabled.
Bits 21:16 – EFS[5:0] Event FIFO Size
The Tx Event FIFO elements are indexed from 0 to EFS - 1.
Value Description
0
Tx Event FIFO disabled
1 - 32
Number of Tx Event FIFO elements.
>32
Values greater than 32 are interpreted as 32.
Bits 15:0 – EFSA[15:0] Event FIFO Start Address
Start address of Tx Event FIFO in Message RAM. When the CAN module addresses the Message RAM it
addresses 32-bit words, not single bytes. The configurable start addresses are 32-bit word addresses, i.e.
only bits 15 to 2 are evaluated, the two least significant bits are ignored. Bits 1 to 0 will always be read
back as “00”.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1299