Datasheet

39.8.40 Tx Buffer Cancellation Request
Name: TXBCR
Offset: 0xD4
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
CRn[31:24]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CRn[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CRn[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CRn[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – CRn[31:0] Cancellation Request
Each Tx Buffer has its own Cancellation Request bit.
Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables
the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set
only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP
is reset.
Value Description
0
No cancellation pending.
1
Cancellation pending.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1294