Datasheet

39.8.32 Rx FIFO 1 Status
Name: RXF1S
Offset: 0xB4
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
DMS[1:0] RF1L F1F
Access
R R R R
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
F1PI[5:0]
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
F1GI[5:0]
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
F1FL[6:0]
Access
R R R R R R R
Reset 0 0 0 0 0 0 0
Bits 31:30 – DMS[1:0] Debug Message Status
This field defines the debug message status.
Value Name Description
0x0
IDLE Idle state, wait for reception of debug messages, DMA request is cleared.
0x1
DBGA Debug message A received.
0x2
DBGB Debug message A, B received.
0x3
DBGC Debug message A, B, C received, DMA request is set.
Bit 25 – RF1L Rx FIFO 1 Message Lost
This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
Overwriting the oldest message when RXF1C.F0OM = ‘1’ will not set this flag.
Value Description
0
No Rx FIFO 1 message lost.
1
Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero.
Bit 24 – F1F Rx FIFO 1 Full
Value Description
0
Rx FIFO 1 not full.
1
Rx FIFO 1 full.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1282