Datasheet

Table Of Contents
39.8.27 Rx FIFO 0 Configuration
Name:  RXF0C
Offset:  0xA0
Reset:  0x00000000
Property:  Write-restricted
Bit 31 30 29 28 27 26 25 24
F0OM F0WM[6:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
F0S[6:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
F0SA[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
F0SA[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 31 – F0OM FIFO 0 Operation Mode
FIFO 0 can be operated in blocking or in overwrite mode.
Value Description
0
FIFO 0 blocking mode.
1
FIFO 0 overwrite mode.
Bits 30:24 – F0WM[6:0] Rx FIFO 0 Watermark
Value Description
0
Watermark interrupt disabled.
1 - 64
Level for Rx FIFO 0 watermark interrupt (IR.RF0W).
>64
Watermark interrupt disabled.
Bits 22:16 – F0S[6:0] Rx FIFO 0 Size
The Rx FIFO 0 elements are indexed from 0 to F0S - 1.
Value Description
0
No Rx FIFO 0
1 - 64
Number of Rx FIFO 0 elements.
>64
Values greater than 64 are interpreted as 64.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1275