Datasheet

39.8.17 Interrupt Enable
Name: IE
Offset: 0x54
Reset: 0x00000000
Property: -
The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will
be signalled on an interrupt line.
Bit 31 30 29 28 27 26 25 24
ARAE PEDE PEAE WDIE BOE EWE
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
EPE ELOE BEUE BECE DRXE TOOE MRAFE TSWE
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TEFLE TEFFE TEFWE TEFNE TFEE TCFE TCE HPME
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RF1LE RF1FE RF1WE RF1NE RF0LE RF0FE RF0WE RF0NE
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 29 – ARAE Access to Reserved Address Interrupt Enable
Value Description
0
Interrupt disabled.
1
Interrupt enabled.
Bit 28 – PEDE Protocol Error in Data Phase Interrupt Enable
Value Description
0
Interrupt disabled.
1
Interrupt enabled.
Bit 27 – PEAE Protocol Error in Arbitration Phase Interrupt Enable
Value Description
0
Interrupt disabled.
1
Interrupt enabled.
Bit 26 – WDIE Watchdog Interrupt Enable
Value Description
0
Interrupt disabled.
1
Interrupt enabled.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1258