Datasheet

39.8.16 Interrupt
Name: IR
Offset: 0x50
Reset: 0x00000000
Property: -
The flags are set when one of the listed conditions is detected (edge-sensitive). A flag is cleared by
writing a 1 to the corresponding bit field. Writing a 0 has no effect. A hard reset will clear the register.
Bit 31 30 29 28 27 26 25 24
ARA PED PEA WDI BO EW
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
EP ELO BEU BEC DRX TOO MRAF TSW
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TEFL TEFF TEFW TEFN TFE TCF TC HPM
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RF1L RF1F RF1W RF1N RF0L RF0F RF0W RF0N
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 29 – ARA Access to Reserved Address
Value Description
0
No access to reserved address occurred.
1
Access to reserved address occurred.
Bit 28 – PED Protocol Error in Data Phase
Value Description
0
No protocol error in data phase.
1
Protocol error in data phase detected (PSR.DLEC != 0,7).
Bit 27 – PEA Protocol Error in Arbitration Phase
Value Description
0
No protocol error in arbitration phase.
1
Protocol error in arbitration phase detected (PSR.LEC != 0,7).
Bit 26 – WDI Watchdog Interrupt
Value Description
0
No Message RAM Watchdog event occurred.
1
Message RAM Watchdog event due to missing READY.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1254