Datasheet

39.8.7 CC Control
Name: CCCR
Offset: 0x18
Reset: 0x00000001
Property: Read-only, Write-restricted
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
TXP EFBI PXHD BRSE FDOE
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TEST DAR MON CSR CSA ASM CCE INIT
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 1
Bit 14 – TXP Transmit Pause
This bit field is write-restricted and only writable if bit fields CCE = 1 and INIT = 1.
Value Description
0
Transmit pause disabled.
1
Transmit pause enabled. The CAN pauses for two CAN bit times before starting the next
transmission after itself has successfully transmitted a frame.
Bit 13 – EFBI Edge Filtering during Bus Integration
Value Description
0
Edge filtering is disabled.
1
Two consecutive dominant tq required to detect an edge for hard synchronization.
Bit 12 – PXHD Protocol Exception Handling Disable
Note: When protocol exception handling is disabled, the CAN will transmit an error frame when it
detects a protocol exception condition.
Value Description
0
Protocol exception handling enabled.
1
Protocol exception handling disabled.
Bit 9 – BRSE Bit Rate Switch Enable
Note: When CAN FD operation is disabled FDOE = 0, BRSE is not evaluated.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1240