Datasheet

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Offset Name Bit Pos.
0xD8 TXBTO
7:0 TOn[7:0]
15:8 TOn[15:8]
23:16 TOn[23:16]
31:24 TOn[31:24]
0xDC TXBCF
7:0 CFn[7:0]
15:8 CFn[15:8]
23:16 CFn[23:16]
31:24 CFn[31:24]
0xE0 TXBTIE
7:0 TIEn[7:0]
15:8 TIEn[15:8]
23:16 TIEn[23:16]
31:24 TIEn[31:24]
0xE4 TXBCIE
7:0 CFIEn[7:0]
15:8 CFIEn[15:8]
23:16 CFIEn[23:16]
31:24 CFIEn[31:24]
0xE8
...
0xEF
Reserved
0xF0 TXEFC
7:0 EFSA[7:0]
15:8 EFSA[15:8]
23:16 EFS[5:0]
31:24 EFWM[5:0]
0xF4 TXEFS
7:0 EFFL[4:0]
15:8 EFGI[4:0]
23:16 EFPI[4:0]
31:24 TEFL EFF
0xF8 TXEFA
7:0 EFAI[4:0]
15:8
23:16
31:24
39.8 Register Description
Registers are 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed
directly.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1232