Datasheet

register (CCCR.CSR = 1). Once all pending transactions are completed and the idle bus state is
detected, the CAN will automatically set the Clock Stop Acknowledge bit (CCCR.CSA = 1). The CAN then
reverts back to its initial state (CCCR.INIT = 1), blocking further transfers, and it is now safe for
CLK_CANx_APB and GCLK_CANx to be switched off and the system may go to standby.
To leave low power mode, CLK_CANx_APB and GCLK_CANx must be active before writing CCCR.CSR
to '0'. The CAN will acknowledge this by resetting CCCR.CSA = 0. Afterwards, the application can restart
CAN communication by resetting bit CCCR.INIT.
39.6.10 Synchronization
Due to the asynchronicity between the main clock domain (CLK_CAN_APB) and the peripheral clock
domain (GCLK_CAN) some registers are synchronized when written. When a write-synchronized register
is written, the read back value will not be updated until the register has completed synchronization.
The following bits and registers are write-synchronized:
l Initialization bit in CC Control register (CCCR.INIT)
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
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Datasheet
DS60001507E-page 1227