Datasheet

• Tx Buffer with lowest Message ID gets highest priority and is transmitted next
39.6.6.7 Transmit Cancellation
The CAN supports transmit cancellation. This feature is especially intended for gateway applications and
AUTOSAR based applications. To cancel a requested transmission from a dedicated Tx Buffer or a Tx
Queue Buffer the CPU has to write a ‘1’ to the corresponding bit position (=number of Tx Buffer) of
register TXBCR. Transmit cancellation is not intended for Tx FIFO operation.
Successful cancellation is signaled by setting the corresponding bit of register TXBCF to ‘1’.
In case a transmit cancellation is requested while a transmission from a Tx Buffer is already ongoing, the
corresponding TXBRP bit remains set as long as the transmission is in progress. If the transmission was
successful, the corresponding TXBTO and TXBCF bits are set. If the transmission was not successful, it
is not repeated and only the corresponding TXBCF bit is set.
Note: In case a pending transmission is canceled immediately before this transmission could have been
started, there follows a short time window where no transmission is started even if another message is
also pending in this node. This may enable another node to transmit a message which may have a lower
priority than the second message in this node.
39.6.6.8 Tx Event Handling
To support Tx event handling the CAN has implemented a Tx Event FIFO. After the CAN has transmitted
a message on the CAN bus, Message ID and timestamp are stored in a Tx Event FIFO element. To link a
Tx event to a Tx Event FIFO element, the Message Marker from the transmitted Tx Buffer is copied into
the Tx Event FIFO element.
The Tx Event FIFO can be configured to a maximum of 32 elements. The Tx Event FIFO element is
described in 39.9.4 Tx Event FIFO Element.
When a Tx Event FIFO full condition is signaled by IR.TEFF, no further elements are written to the Tx
Event FIFO until at least one element has been read out and the Tx Event FIFO Get Index has been
incremented. In case a Tx event occurs while the Tx Event FIFO is full, this event is discarded and
interrupt flag IR.TEFL is set.
To avoid a Tx Event FIFO overflow, the Tx Event FIFO watermark can be used. When the Tx Event FIFO
fill level reaches the Tx Event FIFO watermark configured by TXEFC.EFWM, interrupt flag IR.TEFW is
set.
When reading from the Tx Event FIFO, two times the Tx Event FIFO Get Index TXEFS.EFGI has to be
added to the Tx Event FIFO start address TXEFC.EFSA.
39.6.7 FIFO Acknowledge Handling
The Get Indexes of Rx FIFO 0, Rx FIFO 1 and the Tx Event FIFO are controlled by writing to the
corresponding FIFO Acknowledge Index (refer to 39.8.29 RXF0A, 39.8.33 RXF1A and 39.8.47 TXEFA).
Writing to the FIFO Acknowledge Index will set the FIFO Get Index to the FIFO Acknowledge Index plus
one and thereby updates the FIFO Fill Level. There are two use cases:
When only a single element has been read from the FIFO (the one being pointed to by the Get Index),
this Get Index value is written to the FIFO Acknowledge Index.
When a sequence of elements has been read from the FIFO, it is sufficient to write the FIFO
Acknowledge Index only once at the end of that read sequence (value: Index of the last element read), to
update the FIFO’s Get Index.
Due to the fact that the CPU has free access to the CAN’s Message RAM, special care has to be taken
when reading FIFO elements in an arbitrary order (Get Index not considered). This might be useful when
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1225