Datasheet

multiple Queue Buffers are configured with the same Message ID, the Queue Buffer with the lowest buffer
number is transmitted first.
New messages have to be written to the Tx Buffer referenced by the Put Index TXFQS.TFQPI. An Add
Request cyclically increments the Put Index to the next free Tx Buffer. In case that the Tx Queue is full
(TXFQS.TFQF = ’1’), the Put Index is not valid and no further message should be written to the Tx Queue
until at least one of the requested messages has been sent out or a pending transmission request has
been canceled.
The application may use register TXBRP instead of the Put Index and may place messages to any Tx
Buffer without pending transmission request.
A Tx Queue Buffer allocates Element Size 32-bit words in the Message RAM (refer to Table 39-7).
Therefore the start address of the next available (free) Tx Queue Buffer is calculated by adding Tx FIFO/
Queue Put Index TXFQS.TFQPI (0…31) • Element Size to the Tx Buffer Start Address TXBC.TBSA.
39.6.6.5 Mixed Dedicated Tx Buffers / Tx FIFO
In this case the Tx Buffers section in the Message RAM is subdivided into a set of Dedicated Tx Buffers
and a Tx FIFO. The number of Dedicated Tx Buffers is configured by TXBC.NDTB. The number of Tx
Buffers assigned to the Tx FIFO is configured by TXBC.TFQS. In case TXBC.TFQS is programmed to
zero, only Dedicated Tx Buffers are used.
Figure 39-10. Example of mixed Configuration Dedicated Tx Buffers / Tx FIFO
Dedicated Tx Buffers
Tx FIFO
Buffer Index
Tx Sequence
Get Index
Put Index
1 2
3
4
5 6
7
8 9
1.
5.
4.
6. 2. 3.
ID3 ID15 ID8
ID4
ID2ID24
0
Tx prioritization:
• Scan Dedicated Tx Buffers and oldest pending Tx FIFO Buffer (referenced by TXFS.TFGI)
• Buffer with lowest Message ID gets highest priority and is transmitted next
39.6.6.6 Mixed Dedicated Tx Buffers / Tx Queue
In this case the Tx Buffers section in the Message RAM is subdivided into a set of Dedicated Tx Buffers
and a Tx Queue. The number of Dedicated Tx Buffers is configured by TXBC.NDTB. The number of Tx
Queue Buffers is configured by TXBC.TFQS. In case TXBC.TFQS is programmed to zero, only Dedicated
Tx Buffers are used.
Figure 39-11. Example of mixed Configuration Dedicated Tx Buffers / Tx Queue
Dedicated Tx Buffers
Tx Queue
ID3 ID15 ID8
ID4
ID2ID24
0
1 2
3
4
5 6
7
8 9
Buffer Index
Tx Sequence
2.
5.
4.
6. 3. 1.
Put Index
Tx prioritization:
• Scan all Tx Buffers with activated transmission request
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1224