Datasheet

When an Rx FIFO full condition (RXFnS.FnPI = RXFnS.FnGI) is signaled by RXFnS.FnF = ‘1’, the next
message accepted for the FIFO will overwrite the oldest FIFO message. Put and get index are both
incremented by one.
When an Rx FIFO is operated in overwrite mode and an Rx FIFO full condition is signaled, reading of the
Rx FIFO elements should start at least at get index + 1. The reason for that is, that it might happen, that a
received message is written to the Message RAM (put index) while the CPU is reading from the Message
RAM (get index). In this case inconsistent data may be read from the respective Rx FIFO element.
Adding an offset to the get index when reading from the Rx FIFO avoids this problem. The offset depends
on how fast the CPU accesses the Rx FIFO. The figure below shows an offset of two with respect to the
get index when reading the Rx FIFO. In this case the two messages stored in element 1 and 2 are lost.
Figure 39-8. Rx FIFO Overflow Handling
RXFnS.FnPI =
RXFnS.FnGI
read Get Index + 2
element 0 overwritten
RXFnS.FnPI =
RXFnS.FnGI
Rx FIFO Full
(RXFnS.FnF = '1')
Rx FIFO Overwrite
(RXFnS.FnF = '1')
1
0
2
3
4
5
6
7
1
0
2
3
4
5
6
7
After reading from the Rx FIFO, the number of the last element read has to be written to the Rx FIFO
Acknowledge Index RXFnA.FnA. This increments the get index to that element number. In case the put
index has not been incremented to this Rx FIFO element, the Rx FIFO full condition is reset (RXFnS.FnF
= ‘0’).
39.6.5.3 Dedicated Rx Buffers
The CAN supports up to 64 dedicated Rx Buffers. The start address of the dedicated Rx Buffer section is
configured via RXBC.RBSA.
For each Rx Buffer a Standard or Extended Message ID Filter Element with SFEC / EFEC = “111” and
SFID2 / EFID2[10:9] = “00” has to be configured (see 39.9.5 Standard Message ID Filter Element and
39.9.6 Extended Message ID Filter Element).
After a received message has been accepted by a filter element, the message is stored into the Rx Buffer
in the Message RAM referenced by the filter element. The format is the same as for an Rx FIFO element.
In addition the flag IR.DRX (Message stored in Dedicated Rx Buffer) in the interrupt register is set.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1219