Datasheet

the CAN Core to the Message RAM as well as providing receive message status information. The Tx
Handler is responsible for the transfer of transmit messages from the Message RAM to the CAN Core as
well as providing transmit status information.
Acceptance filtering is implemented by a combination of up to 128 filter elements where each one can be
configured as a range, as a bit mask, or as a dedicated ID filter.
39.6.2 Operating Modes
39.6.2.1 Software Initialization
Software initialization is started by setting bit CCCR.INIT, either by software or by a hardware reset, when
an uncorrected bit error was detected in the Message RAM, or by going Bus_Off. While CCCR.INIT is
set, message transfer from and to the CAN bus is stopped, the status of the CAN bus output CAN_TX
is ”recessive” (HIGH). The counters of the Error Management Logic EML are unchanged. Setting
CCCR.INIT does not change any configuration register. Resetting CCCR.INIT finishes the software
initialization. Afterwards the Bit Stream Processor BSP synchronizes itself to the data transfer on the CAN
bus by waiting for the occurrence of a sequence of 11 consecutive ”recessive” bits (= Bus_Idle) before it
can take part in bus activities and start the message transfer.
Access to the CAN configuration registers is only enabled when both bits CCCR.INIT and CCCR.CCE are
set (protected write).
CCCR.CCE can only be set/reset while CCCR.INIT = ‘1’. CCCR.CCE is automatically reset when
CCCR.INIT is reset.
The following registers are reset when CCCR.CCE is set
• HPMS - High Priority Message Status
• RXF0S - Rx FIFO 0 Status
• RXF1S - Rx FIFO 1 Status
• TXFQS - Tx FIFO/Queue Status
• TXBRP - Tx Buffer Request Pending
• TXBTO - Tx Buffer Transmission Occurred
• TXBCF - Tx Buffer Cancellation Finished
• TXEFS - Tx Event FIFO Status
The Timeout Counter value TOCV.TOC is preset to the value configured by TOCC.TOP when
CCCR.CCE is set.
In addition the state machines of the Tx Handler and Rx Handler are held in idle state while CCCR.CCE =
‘1’.
The following registers are only writable while CCCR.CCE = ‘0’
• TXBAR - Tx Buffer Add Request
• TXBCR - Tx Buffer Cancellation Request
CCCR.TEST and CCCR.MON can only be set by the CPU while CCCR.INIT = ‘1’ and CCR.CCE = ‘1’.
Both bits may be reset at any time. CCCR.DAR can only be set/reset while CCCR.INIT = ‘1’ and
CCCR.CCE = ‘1’.
39.6.2.2 Normal Operation
Once the CAN is initialized and CCCR.INIT is reset to ‘0’, the CAN synchronizes itself to the CAN bus
and is ready for communication.
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1207