Datasheet

39.6.9 Sleep Mode Operation
39.5.3 Clocks
An AHB clock (CLK_CAN_AHB) is required to clock the CAN. This clock can be configured in the Main
Clock peripheral (MCLK) before using the CAN, and the default state of CLK_CAN_AHB can be found in
the MCLK.AHBMASK register.
A generic clock (GCLK_CAN) is required to clock the CAN. This clock must be configured and enabled in
the generic clock controller before using the CAN.
This generic clock is asynchronous to the bus clock (CLK_CAN_AHB). Due to this asynchronicity, writes
to certain registers will require synchronization between the clock domains.
Related Links
15.6.2.6 Peripheral Clock Masking
14. GCLK - Generic Clock Controller
39.5.4 DMA
The CAN has a built-in Direct Memory Access (DMA) and will read/write data to/from the system RAM
when a CAN transaction takes place. No CPU or DMA Controller (DMAC) resources are required.
The DMAC can be used for debug messages functionality.
Related Links
22. DMAC – Direct Memory Access Controller
39.5.5 Interrupts
The interrupt request lines are connected to the interrupt controller. Using the CAN interrupts requires the
interrupt controller to be configured first.
39.5.6 Events
Not applicable.
39.5.7 Debug Operation
Not applicable.
39.5.8 Register Access Protection
Not applicable.
39.5.9 Analog Connections
No analog connections.
39.6 Functional Description
39.6.1 Principle of Operation
The CAN performs communication according to ISO 11898-1:2015 (identical to Bosch CAN protocol
specification 2.0 part A,B, ISO CAN FD).
The message storage is intended to be a single- or dual-ported Message RAM outside the module. It is
connected to the CAN via AHB.
All functions concerning the handling of messages are implemented by the Rx Handler and the Tx
Handler. The Rx Handler manages message acceptance filtering, the transfer of received messages from
SAM D5x/E5x Family Data Sheet
CAN - Control Area Network
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 1206