Datasheet

...........continued
Offset Name Bit Pos.
0x1FE4 PID1
7:0 JEPIDCL[3:0] PARTNBH[3:0]
15:8
23:16
31:24
0x1FE8 PID2
7:0 REVISION[3:0] JEPU JEPIDCH[2:0]
15:8
23:16
31:24
0x1FEC PID3
7:0 REVAND[3:0] CUSMOD[3:0]
15:8
23:16
31:24
0x1FF0 CID0
7:0 PREAMBLEB0[7:0]
15:8
23:16
31:24
0x1FF4 CID1
7:0 CCLASS[3:0] PREAMBLE[3:0]
15:8
23:16
31:24
0x1FF8 CID2
7:0 PREAMBLEB2[7:0]
15:8
23:16
31:24
0x1FFC CID3
7:0 PREAMBLEB3[7:0]
15:8
23:16
31:24
12.13 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 12.5.7 Register Access Protection.
SAM D5x/E5x Family Data Sheet
DSU - Device Service Unit
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 118